{ "design": { "design_info": { "boundary_crc": "0x499C68C943DC87C8", "name": "PCIe_Test", "synth_flow_mode": "Hierarchical", "validated": "true" }, "design_tree": { "processing_system7_0": "", "axi_pcie_0": "", "xlconstant_0": "", "proc_sys_reset_0": "", "proc_sys_reset_1": "", "axi_cdma_0": "", "xlconcat_0": "", "axi_interconnect_0": { "xbar": "", "s00_couplers": {}, "s01_couplers": {}, "m00_couplers": { "auto_ds": "", "auto_pc": "" } }, "axi_interconnect_1": { "xbar": "", "s00_couplers": { "auto_pc": "", "auto_us": "" }, "s01_couplers": {}, "m00_couplers": {}, "m01_couplers": { "auto_cc": "", "auto_ds": "", "auto_pc": "" }, "m02_couplers": { "auto_ds": "", "auto_pc": "" } }, "axi_interconnect_2": { "xbar": "", "s00_couplers": {}, "m00_couplers": {}, "m01_couplers": {} } }, "interface_ports": { "DDR": { "mode": "Master", "vlnv": "xilinx.com:interface:ddrx_rtl:1.0", "parameters": { "AXI_ARBITRATION_SCHEME": { "value": "TDM", "value_src": "default" }, "BURST_LENGTH": { "value": "8", "value_src": "default" }, "CAN_DEBUG": { "value": "false", "value_src": "default" }, "CAS_LATENCY": { "value": "11", "value_src": "default" }, "CAS_WRITE_LATENCY": { "value": "11", "value_src": "default" }, "CS_ENABLED": { "value": "true", "value_src": "default" }, "DATA_MASK_ENABLED": { "value": "true", "value_src": "default" }, "DATA_WIDTH": { "value": "8", "value_src": "default" }, "MEMORY_TYPE": { "value": "COMPONENTS", "value_src": "default" }, "MEM_ADDR_MAP": { "value": "ROW_COLUMN_BANK", "value_src": "default" }, "SLOT": { "value": "Single", "value_src": "default" }, "TIMEPERIOD_PS": { "value": "1250", "value_src": "default" } } }, "FIXED_IO": { "mode": "Master", "vlnv": "xilinx.com:display_processing_system7:fixedio_rtl:1.0", "parameters": { "CAN_DEBUG": { "value": "false", "value_src": "default" } } }, "pcie_7x_mgt": { "mode": "Master", "vlnv": "xilinx.com:interface:pcie_7x_mgt_rtl:1.0" } }, "ports": { "perst": { "type": "rst", "direction": "O", "left": "0", "right": "0", "parameters": { "INSERT_VIP": { "value": "0", "value_src": "default" }, "POLARITY": { "value": "ACTIVE_HIGH", "value_src": "const_prop" } } } }, "components": { "processing_system7_0": { "vlnv": "xilinx.com:ip:processing_system7:5.5", "xci_name": "zynq_default_processing_system7_0_0", "parameters": { "PCW_ACT_APU_PERIPHERAL_FREQMHZ": { "value": "666.666687" }, "PCW_ACT_CAN_PERIPHERAL_FREQMHZ": { "value": "10.000000" }, "PCW_ACT_DCI_PERIPHERAL_FREQMHZ": { "value": "10.158730" }, "PCW_ACT_ENET0_PERIPHERAL_FREQMHZ": { "value": "10.000000" }, "PCW_ACT_ENET1_PERIPHERAL_FREQMHZ": { "value": "10.000000" }, "PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ": { "value": "100.000000" }, "PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ": { "value": "250.000000" }, "PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ": { "value": "10.000000" }, "PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ": { "value": "10.000000" }, "PCW_ACT_PCAP_PERIPHERAL_FREQMHZ": { "value": "200.000000" }, "PCW_ACT_QSPI_PERIPHERAL_FREQMHZ": { "value": "10.000000" }, "PCW_ACT_SDIO_PERIPHERAL_FREQMHZ": { "value": "10.000000" }, "PCW_ACT_SMC_PERIPHERAL_FREQMHZ": { "value": "10.000000" }, "PCW_ACT_SPI_PERIPHERAL_FREQMHZ": { "value": "10.000000" }, "PCW_ACT_TPIU_PERIPHERAL_FREQMHZ": { "value": "200.000000" }, "PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ": { "value": "111.111115" }, "PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ": { "value": "111.111115" }, "PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ": { "value": "111.111115" }, "PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ": { "value": "111.111115" }, "PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ": { "value": "111.111115" }, "PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ": { "value": "111.111115" }, "PCW_ACT_UART_PERIPHERAL_FREQMHZ": { "value": "100.000000" }, "PCW_ACT_WDT_PERIPHERAL_FREQMHZ": { "value": "111.111115" }, "PCW_CLK0_FREQ": { "value": "100000000" }, "PCW_CLK1_FREQ": { "value": "250000000" }, "PCW_CLK2_FREQ": { "value": "10000000" }, "PCW_CLK3_FREQ": { "value": "10000000" }, "PCW_DDR_RAM_HIGHADDR": { "value": "0x3FFFFFFF" }, "PCW_ENET0_PERIPHERAL_CLKSRC": { "value": "IO PLL" }, "PCW_ENET0_PERIPHERAL_ENABLE": { "value": "0" }, "PCW_EN_CLK0_PORT": { "value": "1" }, "PCW_EN_CLK1_PORT": { "value": "1" }, "PCW_EN_CLKTRIG0_PORT": { "value": "0" }, "PCW_EN_EMIO_ENET0": { "value": "0" }, "PCW_EN_EMIO_GPIO": { "value": "0" }, "PCW_EN_EMIO_UART0": { "value": "0" }, "PCW_EN_ENET0": { "value": "0" }, "PCW_EN_QSPI": { "value": "0" }, "PCW_EN_RST0_PORT": { "value": "1" }, "PCW_EN_SDIO0": { "value": "0" }, "PCW_EN_UART0": { "value": "1" }, "PCW_EN_UART1": { "value": "0" }, "PCW_FCLK_CLK0_BUF": { "value": "FALSE" }, "PCW_FCLK_CLK1_BUF": { "value": "TRUE" }, "PCW_FPGA0_PERIPHERAL_FREQMHZ": { "value": "100" }, "PCW_FPGA1_PERIPHERAL_FREQMHZ": { "value": "250" }, "PCW_FPGA_FCLK0_ENABLE": { "value": "1" }, "PCW_FPGA_FCLK1_ENABLE": { "value": "1" }, "PCW_GPIO_EMIO_GPIO_ENABLE": { "value": "0" }, "PCW_IRQ_F2P_INTR": { "value": "1" }, "PCW_MIO_14_IOTYPE": { "value": "LVCMOS 3.3V" }, "PCW_MIO_14_PULLUP": { "value": "enabled" }, "PCW_MIO_14_SLEW": { "value": "slow" }, "PCW_MIO_15_IOTYPE": { "value": "LVCMOS 3.3V" }, "PCW_MIO_15_PULLUP": { "value": "enabled" }, "PCW_MIO_15_SLEW": { "value": "slow" }, "PCW_MIO_TREE_PERIPHERALS": { "value": "unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#UART 0#UART 0#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned" }, "PCW_MIO_TREE_SIGNALS": { "value": "unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#rx#tx#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned" }, "PCW_NAND_PERIPHERAL_ENABLE": { "value": "0" }, "PCW_NOR_PERIPHERAL_ENABLE": { "value": "0" }, "PCW_PRESET_BANK1_VOLTAGE": { "value": "LVCMOS 1.8V" }, "PCW_QSPI_PERIPHERAL_ENABLE": { "value": "0" }, "PCW_SD0_PERIPHERAL_ENABLE": { "value": "0" }, "PCW_SDIO_PERIPHERAL_VALID": { "value": "0" }, "PCW_UART0_GRP_FULL_ENABLE": { "value": "0" }, "PCW_UART0_PERIPHERAL_ENABLE": { "value": "1" }, "PCW_UART0_UART0_IO": { "value": "MIO 14 .. 15" }, "PCW_UART1_PERIPHERAL_ENABLE": { "value": "0" }, "PCW_UART_PERIPHERAL_FREQMHZ": { "value": "100" }, "PCW_UART_PERIPHERAL_VALID": { "value": "1" }, "PCW_UIPARAM_ACT_DDR_FREQ_MHZ": { "value": "533.333374" }, "PCW_UIPARAM_DDR_PARTNO": { "value": "MT41J256M16 RE-125" }, "PCW_USE_FABRIC_INTERRUPT": { "value": "1" }, "PCW_USE_M_AXI_GP0": { "value": "1" }, "PCW_USE_S_AXI_HP0": { "value": "1" } } }, "axi_pcie_0": { "vlnv": "xilinx.com:ip:axi_pcie:2.9", "xci_name": "zynq_default_axi_pcie_0_0", "parameters": { "BAR0_SCALE": { "value": "Gigabytes" }, "BAR0_SIZE": { "value": "1" }, "BASEADDR": { "value": "0x00000000" }, "BASE_CLASS_MENU": { "value": "Bridge_device" }, "CLASS_CODE": { "value": "0x060400" }, "DEVICE_ID": { "value": "0x7124" }, "HIGHADDR": { "value": "0x001FFFFF" }, "INCLUDE_RC": { "value": "Root_Port_of_PCI_Express_Root_Complex" }, "MAX_LINK_SPEED": { "value": "5.0_GT/s" }, "M_AXI_DATA_WIDTH": { "value": "128" }, "NO_OF_LANES": { "value": "X4" }, "REF_CLK_FREQ": { "value": "100_MHz" }, "SLOT_CLOCK_CONFIG": { "value": "false" }, "SUB_CLASS_INTERFACE_MENU": { "value": "InfiniBand_to_PCI_host_bridge" }, "S_AXI_DATA_WIDTH": { "value": "128" } } }, "xlconstant_0": { "vlnv": "xilinx.com:ip:xlconstant:1.1", "xci_name": "zynq_default_xlconstant_0_0", "parameters": { "CONST_VAL": { "value": "0" } } }, "proc_sys_reset_0": { "vlnv": "xilinx.com:ip:proc_sys_reset:5.0", "xci_name": "zynq_default_proc_sys_reset_0_0" }, "proc_sys_reset_1": { "vlnv": "xilinx.com:ip:proc_sys_reset:5.0", "xci_name": "zynq_default_proc_sys_reset_0_1" }, "axi_cdma_0": { "vlnv": "xilinx.com:ip:axi_cdma:4.1", "xci_name": "zynq_default_axi_cdma_0_0", "parameters": { "C_INCLUDE_DRE": { "value": "0" }, "C_INCLUDE_SF": { "value": "0" }, "C_INCLUDE_SG": { "value": "0" }, "C_M_AXI_DATA_WIDTH": { "value": "128" }, "C_M_AXI_MAX_BURST_LEN": { "value": "4" }, "C_USE_DATAMOVER_LITE": { "value": "0" } } }, "xlconcat_0": { "vlnv": "xilinx.com:ip:xlconcat:2.1", "xci_name": "zynq_default_xlconcat_0_0" }, "axi_interconnect_0": { "vlnv": "xilinx.com:ip:axi_interconnect:2.1", "xci_name": "zynq_default_axi_interconnect_0_0", "parameters": { "NUM_MI": { "value": "1" }, "NUM_SI": { "value": "2" } }, "interface_ports": { "S00_AXI": { "mode": "Slave", "vlnv": "xilinx.com:interface:aximm_rtl:1.0" }, "M00_AXI": { "mode": "Master", "vlnv": "xilinx.com:interface:aximm_rtl:1.0" }, "S01_AXI": { "mode": "Slave", "vlnv": "xilinx.com:interface:aximm_rtl:1.0" } }, "ports": { "ACLK": { "type": "clk", "direction": "I", "parameters": { "ASSOCIATED_RESET": { "value": "ARESETN" } } }, "ARESETN": { "type": "rst", "direction": "I" }, "S00_ACLK": { "type": "clk", "direction": "I", "parameters": { "ASSOCIATED_BUSIF": { "value": "S00_AXI" }, "ASSOCIATED_RESET": { "value": "S00_ARESETN" } } }, "S00_ARESETN": { "type": "rst", "direction": "I" }, "M00_ACLK": { "type": "clk", "direction": "I", "parameters": { "ASSOCIATED_BUSIF": { "value": "M00_AXI" }, "ASSOCIATED_RESET": { "value": "M00_ARESETN" } } }, "M00_ARESETN": { "type": "rst", "direction": "I" }, "S01_ACLK": { "type": "clk", "direction": "I", "parameters": { "ASSOCIATED_BUSIF": { "value": "S01_AXI" }, "ASSOCIATED_RESET": { "value": "S01_ARESETN" } } }, "S01_ARESETN": { "type": "rst", "direction": "I" } }, "components": { "xbar": { "vlnv": "xilinx.com:ip:axi_crossbar:2.1", "xci_name": "zynq_default_xbar_0", "parameters": { "NUM_MI": { "value": "1" }, "NUM_SI": { "value": "2" }, "STRATEGY": { "value": "0" } } }, "s00_couplers": { "interface_ports": { "M_AXI": { "mode": "Master", "vlnv": "xilinx.com:interface:aximm_rtl:1.0" }, "S_AXI": { "mode": "Slave", "vlnv": "xilinx.com:interface:aximm_rtl:1.0" } }, "ports": { "M_ACLK": { "type": "clk", "direction": "I", "parameters": { "ASSOCIATED_BUSIF": { "value": "M_AXI" }, "ASSOCIATED_RESET": { "value": "M_ARESETN" } } }, "M_ARESETN": { "type": "rst", "direction": "I" }, "S_ACLK": { "type": "clk", "direction": "I", "parameters": { "ASSOCIATED_BUSIF": { "value": "S_AXI" }, "ASSOCIATED_RESET": { "value": "S_ARESETN" } } }, "S_ARESETN": { "type": "rst", "direction": "I" } }, "interface_nets": { "s00_couplers_to_s00_couplers": { "interface_ports": [ "S_AXI", "M_AXI" ] } } }, "s01_couplers": { "interface_ports": { "M_AXI": { "mode": "Master", "vlnv": "xilinx.com:interface:aximm_rtl:1.0" }, "S_AXI": { "mode": "Slave", "vlnv": "xilinx.com:interface:aximm_rtl:1.0" } }, "ports": { "M_ACLK": { "type": "clk", "direction": "I", "parameters": { "ASSOCIATED_BUSIF": { "value": "M_AXI" }, "ASSOCIATED_RESET": { "value": "M_ARESETN" } } }, "M_ARESETN": { "type": "rst", "direction": "I" }, "S_ACLK": { "type": "clk", "direction": "I", "parameters": { "ASSOCIATED_BUSIF": { "value": "S_AXI" }, "ASSOCIATED_RESET": { "value": "S_ARESETN" } } }, "S_ARESETN": { "type": "rst", "direction": "I" } }, "interface_nets": { "s01_couplers_to_s01_couplers": { "interface_ports": [ "S_AXI", "M_AXI" ] } } }, "m00_couplers": { "interface_ports": { "M_AXI": { "mode": "Master", "vlnv": "xilinx.com:interface:aximm_rtl:1.0" }, "S_AXI": { "mode": "Slave", "vlnv": "xilinx.com:interface:aximm_rtl:1.0" } }, "ports": { "M_ACLK": { "type": "clk", "direction": "I", "parameters": { "ASSOCIATED_BUSIF": { "value": "M_AXI" }, "ASSOCIATED_RESET": { "value": "M_ARESETN" } } }, "M_ARESETN": { "type": "rst", "direction": "I" }, "S_ACLK": { "type": "clk", "direction": "I", "parameters": { "ASSOCIATED_BUSIF": { "value": "S_AXI" }, "ASSOCIATED_RESET": { "value": "S_ARESETN" } } }, "S_ARESETN": { "type": "rst", "direction": "I" } }, "components": { "auto_ds": { "vlnv": "xilinx.com:ip:axi_dwidth_converter:2.1", "xci_name": "zynq_default_auto_ds_0", "parameters": { "MAX_SPLIT_BEATS": { "value": "16" }, "MI_DATA_WIDTH": { "value": "64" }, "SI_DATA_WIDTH": { "value": "128" } } }, "auto_pc": { "vlnv": "xilinx.com:ip:axi_protocol_converter:2.1", "xci_name": "zynq_default_auto_pc_0", "parameters": { "MI_PROTOCOL": { "value": "AXI3" }, "SI_PROTOCOL": { "value": "AXI4" }, "TRANSLATION_MODE": { "value": "0" } } } }, "interface_nets": { "m00_couplers_to_auto_ds": { "interface_ports": [ "S_AXI", "auto_ds/S_AXI" ] }, "auto_ds_to_auto_pc": { "interface_ports": [ "auto_ds/M_AXI", "auto_pc/S_AXI" ] }, "auto_pc_to_m00_couplers": { "interface_ports": [ "M_AXI", "auto_pc/M_AXI" ] } }, "nets": { "S_ACLK_1": { "ports": [ "S_ACLK", "auto_ds/s_axi_aclk", "auto_pc/aclk" ] }, "S_ARESETN_1": { "ports": [ "S_ARESETN", "auto_ds/s_axi_aresetn", "auto_pc/aresetn" ] } } } }, "interface_nets": { "xbar_to_m00_couplers": { "interface_ports": [ "xbar/M00_AXI", "m00_couplers/S_AXI" ] }, "axi_interconnect_0_to_s00_couplers": { "interface_ports": [ "S00_AXI", "s00_couplers/S_AXI" ] }, "s00_couplers_to_xbar": { "interface_ports": [ "s00_couplers/M_AXI", "xbar/S00_AXI" ] }, "axi_interconnect_0_to_s01_couplers": { "interface_ports": [ "S01_AXI", "s01_couplers/S_AXI" ] }, "s01_couplers_to_xbar": { "interface_ports": [ "s01_couplers/M_AXI", "xbar/S01_AXI" ] }, "m00_couplers_to_axi_interconnect_0": { "interface_ports": [ "M00_AXI", "m00_couplers/M_AXI" ] } }, "nets": { "axi_interconnect_0_ACLK_net": { "ports": [ "ACLK", "xbar/aclk", "s00_couplers/M_ACLK", "s01_couplers/M_ACLK", "m00_couplers/S_ACLK" ] }, "axi_interconnect_0_ARESETN_net": { "ports": [ "ARESETN", "xbar/aresetn", "s00_couplers/M_ARESETN", "s01_couplers/M_ARESETN", "m00_couplers/S_ARESETN" ] }, "S00_ACLK_1": { "ports": [ "S00_ACLK", "s00_couplers/S_ACLK" ] }, "S00_ARESETN_1": { "ports": [ "S00_ARESETN", "s00_couplers/S_ARESETN" ] }, "S01_ACLK_1": { "ports": [ "S01_ACLK", "s01_couplers/S_ACLK" ] }, "S01_ARESETN_1": { "ports": [ "S01_ARESETN", "s01_couplers/S_ARESETN" ] }, "M00_ACLK_1": { "ports": [ "M00_ACLK", "m00_couplers/M_ACLK" ] }, "M00_ARESETN_1": { "ports": [ "M00_ARESETN", "m00_couplers/M_ARESETN" ] } } }, "axi_interconnect_1": { "vlnv": "xilinx.com:ip:axi_interconnect:2.1", "xci_name": "zynq_default_axi_interconnect_0_1", "parameters": { "NUM_MI": { "value": "3" }, "NUM_SI": { "value": "2" } }, "interface_ports": { "S00_AXI": { "mode": "Slave", "vlnv": "xilinx.com:interface:aximm_rtl:1.0" }, "M00_AXI": { "mode": "Master", "vlnv": "xilinx.com:interface:aximm_rtl:1.0" }, "S01_AXI": { "mode": "Slave", "vlnv": "xilinx.com:interface:aximm_rtl:1.0" }, "M01_AXI": { "mode": "Master", "vlnv": "xilinx.com:interface:aximm_rtl:1.0" }, "M02_AXI": { "mode": "Master", "vlnv": "xilinx.com:interface:aximm_rtl:1.0" } }, "ports": { "ACLK": { "type": "clk", "direction": "I", "parameters": { "ASSOCIATED_RESET": { "value": "ARESETN" } } }, "ARESETN": { "type": "rst", "direction": "I" }, "S00_ACLK": { "type": "clk", "direction": "I", "parameters": { "ASSOCIATED_BUSIF": { "value": "S00_AXI" }, "ASSOCIATED_RESET": { "value": "S00_ARESETN" } } }, "S00_ARESETN": { "type": "rst", "direction": "I" }, "M00_ACLK": { "type": "clk", "direction": "I", "parameters": { "ASSOCIATED_BUSIF": { "value": "M00_AXI" }, "ASSOCIATED_RESET": { "value": "M00_ARESETN" } } }, "M00_ARESETN": { "type": "rst", "direction": "I" }, "S01_ACLK": { "type": "clk", "direction": "I", "parameters": { "ASSOCIATED_BUSIF": { "value": "S01_AXI" }, "ASSOCIATED_RESET": { "value": "S01_ARESETN" } } }, "S01_ARESETN": { "type": "rst", "direction": "I" }, "M01_ACLK": { "type": "clk", "direction": "I", "parameters": { "ASSOCIATED_BUSIF": { "value": "M01_AXI" }, "ASSOCIATED_RESET": { "value": "M01_ARESETN" } } }, "M01_ARESETN": { "type": "rst", "direction": "I" }, "M02_ACLK": { "type": "clk", "direction": "I", "parameters": { "ASSOCIATED_BUSIF": { "value": "M02_AXI" }, "ASSOCIATED_RESET": { "value": "M02_ARESETN" } } }, "M02_ARESETN": { "type": "rst", "direction": "I" } }, "components": { "xbar": { "vlnv": "xilinx.com:ip:axi_crossbar:2.1", "xci_name": "zynq_default_xbar_1", "parameters": { "NUM_MI": { "value": "3" }, "NUM_SI": { "value": "2" }, "STRATEGY": { "value": "0" } } }, "s00_couplers": { "interface_ports": { "M_AXI": { "mode": "Master", "vlnv": "xilinx.com:interface:aximm_rtl:1.0" }, "S_AXI": { "mode": "Slave", "vlnv": "xilinx.com:interface:aximm_rtl:1.0" } }, "ports": { "M_ACLK": { "type": "clk", "direction": "I", "parameters": { "ASSOCIATED_BUSIF": { "value": "M_AXI" }, "ASSOCIATED_RESET": { "value": "M_ARESETN" } } }, "M_ARESETN": { "type": "rst", "direction": "I" }, "S_ACLK": { "type": "clk", "direction": "I", "parameters": { "ASSOCIATED_BUSIF": { "value": "S_AXI" }, "ASSOCIATED_RESET": { "value": "S_ARESETN" } } }, "S_ARESETN": { "type": "rst", "direction": "I" } }, "components": { "auto_pc": { "vlnv": "xilinx.com:ip:axi_protocol_converter:2.1", "xci_name": "zynq_default_auto_pc_3", "parameters": { "MI_PROTOCOL": { "value": "AXI4" }, "SI_PROTOCOL": { "value": "AXI3" } } }, "auto_us": { "vlnv": "xilinx.com:ip:axi_dwidth_converter:2.1", "xci_name": "zynq_default_auto_us_0", "parameters": { "MI_DATA_WIDTH": { "value": "128" }, "SI_DATA_WIDTH": { "value": "32" } } } }, "interface_nets": { "auto_pc_to_auto_us": { "interface_ports": [ "auto_pc/M_AXI", "auto_us/S_AXI" ] }, "auto_us_to_s00_couplers": { "interface_ports": [ "M_AXI", "auto_us/M_AXI" ] }, "s00_couplers_to_auto_pc": { "interface_ports": [ "S_AXI", "auto_pc/S_AXI" ] } }, "nets": { "S_ACLK_1": { "ports": [ "S_ACLK", "auto_pc/aclk", "auto_us/s_axi_aclk" ] }, "S_ARESETN_1": { "ports": [ "S_ARESETN", "auto_pc/aresetn", "auto_us/s_axi_aresetn" ] } } }, "s01_couplers": { "interface_ports": { "M_AXI": { "mode": "Master", "vlnv": "xilinx.com:interface:aximm_rtl:1.0" }, "S_AXI": { "mode": "Slave", "vlnv": "xilinx.com:interface:aximm_rtl:1.0" } }, "ports": { "M_ACLK": { "type": "clk", "direction": "I", "parameters": { "ASSOCIATED_BUSIF": { "value": "M_AXI" }, "ASSOCIATED_RESET": { "value": "M_ARESETN" } } }, "M_ARESETN": { "type": "rst", "direction": "I" }, "S_ACLK": { "type": "clk", "direction": "I", "parameters": { "ASSOCIATED_BUSIF": { "value": "S_AXI" }, "ASSOCIATED_RESET": { "value": "S_ARESETN" } } }, "S_ARESETN": { "type": "rst", "direction": "I" } }, "interface_nets": { "s01_couplers_to_s01_couplers": { "interface_ports": [ "S_AXI", "M_AXI" ] } } }, "m00_couplers": { "interface_ports": { "M_AXI": { "mode": "Master", "vlnv": "xilinx.com:interface:aximm_rtl:1.0" }, "S_AXI": { "mode": "Slave", "vlnv": "xilinx.com:interface:aximm_rtl:1.0" } }, "ports": { "M_ACLK": { "type": "clk", "direction": "I", "parameters": { "ASSOCIATED_BUSIF": { "value": "M_AXI" }, "ASSOCIATED_RESET": { "value": "M_ARESETN" } } }, "M_ARESETN": { "type": "rst", "direction": "I" }, "S_ACLK": { "type": "clk", "direction": "I", "parameters": { "ASSOCIATED_BUSIF": { "value": "S_AXI" }, "ASSOCIATED_RESET": { "value": "S_ARESETN" } } }, "S_ARESETN": { "type": "rst", "direction": "I" } }, "interface_nets": { "m00_couplers_to_m00_couplers": { "interface_ports": [ "S_AXI", "M_AXI" ] } } }, "m01_couplers": { "interface_ports": { "M_AXI": { "mode": "Master", "vlnv": "xilinx.com:interface:aximm_rtl:1.0" }, "S_AXI": { "mode": "Slave", "vlnv": "xilinx.com:interface:aximm_rtl:1.0" } }, "ports": { "M_ACLK": { "type": "clk", "direction": "I", "parameters": { "ASSOCIATED_BUSIF": { "value": "M_AXI" }, "ASSOCIATED_RESET": { "value": "M_ARESETN" } } }, "M_ARESETN": { "type": "rst", "direction": "I" }, "S_ACLK": { "type": "clk", "direction": "I", "parameters": { "ASSOCIATED_BUSIF": { "value": "S_AXI" }, "ASSOCIATED_RESET": { "value": "S_ARESETN" } } }, "S_ARESETN": { "type": "rst", "direction": "I" } }, "components": { "auto_cc": { "vlnv": "xilinx.com:ip:axi_clock_converter:2.1", "xci_name": "zynq_default_auto_cc_0" }, "auto_ds": { "vlnv": "xilinx.com:ip:axi_dwidth_converter:2.1", "xci_name": "zynq_default_auto_ds_1", "parameters": { "MI_DATA_WIDTH": { "value": "32" }, "SI_DATA_WIDTH": { "value": "128" } } }, "auto_pc": { "vlnv": "xilinx.com:ip:axi_protocol_converter:2.1", "xci_name": "zynq_default_auto_pc_1", "parameters": { "MI_PROTOCOL": { "value": "AXI4LITE" }, "SI_PROTOCOL": { "value": "AXI4" } } } }, "interface_nets": { "m01_couplers_to_auto_cc": { "interface_ports": [ "S_AXI", "auto_cc/S_AXI" ] }, "auto_cc_to_auto_ds": { "interface_ports": [ "auto_cc/M_AXI", "auto_ds/S_AXI" ] }, "auto_pc_to_m01_couplers": { "interface_ports": [ "M_AXI", "auto_pc/M_AXI" ] }, "auto_ds_to_auto_pc": { "interface_ports": [ "auto_ds/M_AXI", "auto_pc/S_AXI" ] } }, "nets": { "M_ACLK_1": { "ports": [ "M_ACLK", "auto_cc/m_axi_aclk", "auto_ds/s_axi_aclk", "auto_pc/aclk" ] }, "S_ACLK_1": { "ports": [ "S_ACLK", "auto_cc/s_axi_aclk" ] }, "M_ARESETN_1": { "ports": [ "M_ARESETN", "auto_cc/m_axi_aresetn", "auto_ds/s_axi_aresetn", "auto_pc/aresetn" ] }, "S_ARESETN_1": { "ports": [ "S_ARESETN", "auto_cc/s_axi_aresetn" ] } } }, "m02_couplers": { "interface_ports": { "M_AXI": { "mode": "Master", "vlnv": "xilinx.com:interface:aximm_rtl:1.0" }, "S_AXI": { "mode": "Slave", "vlnv": "xilinx.com:interface:aximm_rtl:1.0" } }, "ports": { "M_ACLK": { "type": "clk", "direction": "I", "parameters": { "ASSOCIATED_BUSIF": { "value": "M_AXI" }, "ASSOCIATED_RESET": { "value": "M_ARESETN" } } }, "M_ARESETN": { "type": "rst", "direction": "I" }, "S_ACLK": { "type": "clk", "direction": "I", "parameters": { "ASSOCIATED_BUSIF": { "value": "S_AXI" }, "ASSOCIATED_RESET": { "value": "S_ARESETN" } } }, "S_ARESETN": { "type": "rst", "direction": "I" } }, "components": { "auto_ds": { "vlnv": "xilinx.com:ip:axi_dwidth_converter:2.1", "xci_name": "zynq_default_auto_ds_2", "parameters": { "MI_DATA_WIDTH": { "value": "32" }, "SI_DATA_WIDTH": { "value": "128" } } }, "auto_pc": { "vlnv": "xilinx.com:ip:axi_protocol_converter:2.1", "xci_name": "zynq_default_auto_pc_2", "parameters": { "MI_PROTOCOL": { "value": "AXI4LITE" }, "SI_PROTOCOL": { "value": "AXI4" } } } }, "interface_nets": { "m02_couplers_to_auto_ds": { "interface_ports": [ "S_AXI", "auto_ds/S_AXI" ] }, "auto_ds_to_auto_pc": { "interface_ports": [ "auto_ds/M_AXI", "auto_pc/S_AXI" ] }, "auto_pc_to_m02_couplers": { "interface_ports": [ "M_AXI", "auto_pc/M_AXI" ] } }, "nets": { "S_ACLK_1": { "ports": [ "S_ACLK", "auto_ds/s_axi_aclk", "auto_pc/aclk" ] }, "S_ARESETN_1": { "ports": [ "S_ARESETN", "auto_ds/s_axi_aresetn", "auto_pc/aresetn" ] } } } }, "interface_nets": { "s01_couplers_to_xbar": { "interface_ports": [ "s01_couplers/M_AXI", "xbar/S01_AXI" ] }, "m00_couplers_to_axi_interconnect_1": { "interface_ports": [ "M00_AXI", "m00_couplers/M_AXI" ] }, "s00_couplers_to_xbar": { "interface_ports": [ "s00_couplers/M_AXI", "xbar/S00_AXI" ] }, "axi_interconnect_1_to_s01_couplers": { "interface_ports": [ "S01_AXI", "s01_couplers/S_AXI" ] }, "axi_interconnect_1_to_s00_couplers": { "interface_ports": [ "S00_AXI", "s00_couplers/S_AXI" ] }, "xbar_to_m00_couplers": { "interface_ports": [ "xbar/M00_AXI", "m00_couplers/S_AXI" ] }, "m01_couplers_to_axi_interconnect_1": { "interface_ports": [ "M01_AXI", "m01_couplers/M_AXI" ] }, "m02_couplers_to_axi_interconnect_1": { "interface_ports": [ "M02_AXI", "m02_couplers/M_AXI" ] }, "xbar_to_m01_couplers": { "interface_ports": [ "xbar/M01_AXI", "m01_couplers/S_AXI" ] }, "xbar_to_m02_couplers": { "interface_ports": [ "xbar/M02_AXI", "m02_couplers/S_AXI" ] } }, "nets": { "axi_interconnect_1_ACLK_net": { "ports": [ "ACLK", "xbar/aclk", "s00_couplers/M_ACLK", "s01_couplers/M_ACLK", "m00_couplers/S_ACLK", "m01_couplers/S_ACLK", "m02_couplers/S_ACLK" ] }, "axi_interconnect_1_ARESETN_net": { "ports": [ "ARESETN", "xbar/aresetn", "s00_couplers/M_ARESETN", "s01_couplers/M_ARESETN", "m00_couplers/S_ARESETN", "m01_couplers/S_ARESETN", "m02_couplers/S_ARESETN" ] }, "S00_ACLK_1": { "ports": [ "S00_ACLK", "s00_couplers/S_ACLK" ] }, "S00_ARESETN_1": { "ports": [ "S00_ARESETN", "s00_couplers/S_ARESETN" ] }, "S01_ACLK_1": { "ports": [ "S01_ACLK", "s01_couplers/S_ACLK" ] }, "S01_ARESETN_1": { "ports": [ "S01_ARESETN", "s01_couplers/S_ARESETN" ] }, "M00_ACLK_1": { "ports": [ "M00_ACLK", "m00_couplers/M_ACLK" ] }, "M00_ARESETN_1": { "ports": [ "M00_ARESETN", "m00_couplers/M_ARESETN" ] }, "M01_ACLK_1": { "ports": [ "M01_ACLK", "m01_couplers/M_ACLK" ] }, "M01_ARESETN_1": { "ports": [ "M01_ARESETN", "m01_couplers/M_ARESETN" ] }, "M02_ACLK_1": { "ports": [ "M02_ACLK", "m02_couplers/M_ACLK" ] }, "M02_ARESETN_1": { "ports": [ "M02_ARESETN", "m02_couplers/M_ARESETN" ] } } }, "axi_interconnect_2": { "vlnv": "xilinx.com:ip:axi_interconnect:2.1", "xci_name": "zynq_default_axi_interconnect_1_0", "parameters": { "NUM_MI": { "value": "2" }, "NUM_SI": { "value": "1" } }, "interface_ports": { "S00_AXI": { "mode": "Slave", "vlnv": "xilinx.com:interface:aximm_rtl:1.0" }, "M00_AXI": { "mode": "Master", "vlnv": "xilinx.com:interface:aximm_rtl:1.0" }, "M01_AXI": { "mode": "Master", "vlnv": "xilinx.com:interface:aximm_rtl:1.0" } }, "ports": { "ACLK": { "type": "clk", "direction": "I", "parameters": { "ASSOCIATED_RESET": { "value": "ARESETN" } } }, "ARESETN": { "type": "rst", "direction": "I" }, "S00_ACLK": { "type": "clk", "direction": "I", "parameters": { "ASSOCIATED_BUSIF": { "value": "S00_AXI" }, "ASSOCIATED_RESET": { "value": "S00_ARESETN" } } }, "S00_ARESETN": { "type": "rst", "direction": "I" }, "M00_ACLK": { "type": "clk", "direction": "I", "parameters": { "ASSOCIATED_BUSIF": { "value": "M00_AXI" }, "ASSOCIATED_RESET": { "value": "M00_ARESETN" } } }, "M00_ARESETN": { "type": "rst", "direction": "I" }, "M01_ACLK": { "type": "clk", "direction": "I", "parameters": { "ASSOCIATED_BUSIF": { "value": "M01_AXI" }, "ASSOCIATED_RESET": { "value": "M01_ARESETN" } } }, "M01_ARESETN": { "type": "rst", "direction": "I" } }, "components": { "xbar": { "vlnv": "xilinx.com:ip:axi_crossbar:2.1", "xci_name": "zynq_default_xbar_2", "parameters": { "NUM_MI": { "value": "2" }, "NUM_SI": { "value": "1" }, "STRATEGY": { "value": "0" } } }, "s00_couplers": { "interface_ports": { "M_AXI": { "mode": "Master", "vlnv": "xilinx.com:interface:aximm_rtl:1.0" }, "S_AXI": { "mode": "Slave", "vlnv": "xilinx.com:interface:aximm_rtl:1.0" } }, "ports": { "M_ACLK": { "type": "clk", "direction": "I", "parameters": { "ASSOCIATED_BUSIF": { "value": "M_AXI" }, "ASSOCIATED_RESET": { "value": "M_ARESETN" } } }, "M_ARESETN": { "type": "rst", "direction": "I" }, "S_ACLK": { "type": "clk", "direction": "I", "parameters": { "ASSOCIATED_BUSIF": { "value": "S_AXI" }, "ASSOCIATED_RESET": { "value": "S_ARESETN" } } }, "S_ARESETN": { "type": "rst", "direction": "I" } }, "interface_nets": { "s00_couplers_to_s00_couplers": { "interface_ports": [ "S_AXI", "M_AXI" ] } } }, "m00_couplers": { "interface_ports": { "M_AXI": { "mode": "Master", "vlnv": "xilinx.com:interface:aximm_rtl:1.0" }, "S_AXI": { "mode": "Slave", "vlnv": "xilinx.com:interface:aximm_rtl:1.0" } }, "ports": { "M_ACLK": { "type": "clk", "direction": "I", "parameters": { "ASSOCIATED_BUSIF": { "value": "M_AXI" }, "ASSOCIATED_RESET": { "value": "M_ARESETN" } } }, "M_ARESETN": { "type": "rst", "direction": "I" }, "S_ACLK": { "type": "clk", "direction": "I", "parameters": { "ASSOCIATED_BUSIF": { "value": "S_AXI" }, "ASSOCIATED_RESET": { "value": "S_ARESETN" } } }, "S_ARESETN": { "type": "rst", "direction": "I" } }, "interface_nets": { "m00_couplers_to_m00_couplers": { "interface_ports": [ "S_AXI", "M_AXI" ] } } }, "m01_couplers": { "interface_ports": { "M_AXI": { "mode": "Master", "vlnv": "xilinx.com:interface:aximm_rtl:1.0" }, "S_AXI": { "mode": "Slave", "vlnv": "xilinx.com:interface:aximm_rtl:1.0" } }, "ports": { "M_ACLK": { "type": "clk", "direction": "I", "parameters": { "ASSOCIATED_BUSIF": { "value": "M_AXI" }, "ASSOCIATED_RESET": { "value": "M_ARESETN" } } }, "M_ARESETN": { "type": "rst", "direction": "I" }, "S_ACLK": { "type": "clk", "direction": "I", "parameters": { "ASSOCIATED_BUSIF": { "value": "S_AXI" }, "ASSOCIATED_RESET": { "value": "S_ARESETN" } } }, "S_ARESETN": { "type": "rst", "direction": "I" } }, "interface_nets": { "m01_couplers_to_m01_couplers": { "interface_ports": [ "S_AXI", "M_AXI" ] } } } }, "interface_nets": { "xbar_to_m01_couplers": { "interface_ports": [ "xbar/M01_AXI", "m01_couplers/S_AXI" ] }, "axi_interconnect_2_to_s00_couplers": { "interface_ports": [ "S00_AXI", "s00_couplers/S_AXI" ] }, "s00_couplers_to_xbar": { "interface_ports": [ "s00_couplers/M_AXI", "xbar/S00_AXI" ] }, "m00_couplers_to_axi_interconnect_2": { "interface_ports": [ "M00_AXI", "m00_couplers/M_AXI" ] }, "xbar_to_m00_couplers": { "interface_ports": [ "xbar/M00_AXI", "m00_couplers/S_AXI" ] }, "m01_couplers_to_axi_interconnect_2": { "interface_ports": [ "M01_AXI", "m01_couplers/M_AXI" ] } }, "nets": { "axi_interconnect_2_ACLK_net": { "ports": [ "ACLK", "xbar/aclk", "s00_couplers/M_ACLK", "m00_couplers/S_ACLK", "m01_couplers/S_ACLK" ] }, "axi_interconnect_2_ARESETN_net": { "ports": [ "ARESETN", "xbar/aresetn", "s00_couplers/M_ARESETN", "m00_couplers/S_ARESETN", "m01_couplers/S_ARESETN" ] }, "S00_ACLK_1": { "ports": [ "S00_ACLK", "s00_couplers/S_ACLK" ] }, "S00_ARESETN_1": { "ports": [ "S00_ARESETN", "s00_couplers/S_ARESETN" ] }, "M00_ACLK_1": { "ports": [ "M00_ACLK", "m00_couplers/M_ACLK" ] }, "M00_ARESETN_1": { "ports": [ "M00_ARESETN", "m00_couplers/M_ARESETN" ] }, "M01_ACLK_1": { "ports": [ "M01_ACLK", "m01_couplers/M_ACLK" ] }, "M01_ARESETN_1": { "ports": [ "M01_ARESETN", "m01_couplers/M_ARESETN" ] } } } }, "interface_nets": { "axi_pcie_0_M_AXI": { "interface_ports": [ "axi_pcie_0/M_AXI", "axi_interconnect_0/S00_AXI" ] }, "axi_interconnect_0_M00_AXI": { "interface_ports": [ "axi_interconnect_0/M00_AXI", "processing_system7_0/S_AXI_HP0" ] }, "axi_interconnect_1_M02_AXI": { "interface_ports": [ "axi_interconnect_1/M02_AXI", "axi_cdma_0/S_AXI_LITE" ] }, "axi_interconnect_2_M01_AXI": { "interface_ports": [ "axi_interconnect_2/M01_AXI", "axi_interconnect_1/S01_AXI" ] }, "axi_interconnect_2_M00_AXI": { "interface_ports": [ "axi_interconnect_2/M00_AXI", "axi_interconnect_0/S01_AXI" ] }, "processing_system7_0_FIXED_IO": { "interface_ports": [ "FIXED_IO", "processing_system7_0/FIXED_IO" ] }, "processing_system7_0_M_AXI_GP0": { "interface_ports": [ "processing_system7_0/M_AXI_GP0", "axi_interconnect_1/S00_AXI" ] }, "axi_interconnect_1_M00_AXI": { "interface_ports": [ "axi_interconnect_1/M00_AXI", "axi_pcie_0/S_AXI" ] }, "processing_system7_0_DDR": { "interface_ports": [ "DDR", "processing_system7_0/DDR" ] }, "axi_cdma_0_M_AXI": { "interface_ports": [ "axi_cdma_0/M_AXI", "axi_interconnect_2/S00_AXI" ] }, "axi_pcie_0_pcie_7x_mgt": { "interface_ports": [ "pcie_7x_mgt", "axi_pcie_0/pcie_7x_mgt" ] }, "axi_interconnect_1_M01_AXI": { "interface_ports": [ "axi_interconnect_1/M01_AXI", "axi_pcie_0/S_AXI_CTL" ] } }, "nets": { "xlconstant_0_dout": { "ports": [ "xlconstant_0/dout", "axi_pcie_0/INTX_MSI_Request" ] }, "axi_pcie_0_axi_ctl_aclk_out": { "ports": [ "axi_pcie_0/axi_ctl_aclk_out", "proc_sys_reset_0/slowest_sync_clk", "axi_interconnect_1/M01_ACLK" ] }, "axi_pcie_0_mmcm_lock": { "ports": [ "axi_pcie_0/mmcm_lock", "proc_sys_reset_0/dcm_locked", "proc_sys_reset_1/dcm_locked" ] }, "processing_system7_0_FCLK_RESET0_N": { "ports": [ "processing_system7_0/FCLK_RESET0_N", "proc_sys_reset_0/ext_reset_in", "proc_sys_reset_1/ext_reset_in" ] }, "proc_sys_reset_0_peripheral_reset": { "ports": [ "proc_sys_reset_0/peripheral_reset", "perst" ] }, "proc_sys_reset_0_peripheral_aresetn": { "ports": [ "proc_sys_reset_0/peripheral_aresetn", "axi_pcie_0/axi_aresetn", "axi_interconnect_1/M01_ARESETN" ] }, "axi_pcie_0_axi_aclk_out": { "ports": [ "axi_pcie_0/axi_aclk_out", "proc_sys_reset_1/slowest_sync_clk", "processing_system7_0/M_AXI_GP0_ACLK", "processing_system7_0/S_AXI_HP0_ACLK", "axi_cdma_0/m_axi_aclk", "axi_cdma_0/s_axi_lite_aclk", "axi_interconnect_1/ACLK", "axi_interconnect_1/S00_ACLK", "axi_interconnect_1/M00_ACLK", "axi_interconnect_1/S01_ACLK", "axi_interconnect_1/M02_ACLK", "axi_interconnect_0/ACLK", "axi_interconnect_0/S00_ACLK", "axi_interconnect_0/M00_ACLK", "axi_interconnect_0/S01_ACLK", "axi_interconnect_2/ACLK", "axi_interconnect_2/S00_ACLK", "axi_interconnect_2/M00_ACLK", "axi_interconnect_2/M01_ACLK" ] }, "xlconcat_0_dout": { "ports": [ "xlconcat_0/dout", "processing_system7_0/IRQ_F2P" ] }, "axi_pcie_0_interrupt_out": { "ports": [ "axi_pcie_0/interrupt_out", "xlconcat_0/In0" ] }, "axi_cdma_0_cdma_introut": { "ports": [ "axi_cdma_0/cdma_introut", "xlconcat_0/In1" ] }, "proc_sys_reset_1_peripheral_aresetn": { "ports": [ "proc_sys_reset_1/peripheral_aresetn", "axi_cdma_0/s_axi_lite_aresetn", "axi_interconnect_0/S00_ARESETN", "axi_interconnect_0/M00_ARESETN", "axi_interconnect_0/S01_ARESETN", "axi_interconnect_1/S00_ARESETN", "axi_interconnect_1/M00_ARESETN", "axi_interconnect_1/S01_ARESETN", "axi_interconnect_1/M02_ARESETN", "axi_interconnect_2/S00_ARESETN", "axi_interconnect_2/M00_ARESETN", "axi_interconnect_2/M01_ARESETN" ] }, "proc_sys_reset_1_interconnect_aresetn": { "ports": [ "proc_sys_reset_1/interconnect_aresetn", "axi_interconnect_0/ARESETN", "axi_interconnect_1/ARESETN", "axi_interconnect_2/ARESETN" ] }, "processing_system7_0_FCLK_CLK0": { "ports": [ "processing_system7_0/FCLK_CLK0", "axi_pcie_0/REFCLK" ] } }, "addressing": { "/processing_system7_0": { "address_spaces": { "Data": { "range": "4G", "width": "32", "segments": { "SEG_axi_cdma_0_Reg": { "address_block": "/axi_cdma_0/S_AXI_LITE/Reg", "offset": "0x7E200000", "range": "64K" }, "SEG_axi_pcie_0_BAR0": { "address_block": "/axi_pcie_0/S_AXI/BAR0", "offset": "0x40000000", "range": "256M" }, "SEG_axi_pcie_0_CTL0": { "address_block": "/axi_pcie_0/S_AXI_CTL/CTL0", "offset": "0x50000000", "range": "64M" } } } } }, "/axi_pcie_0": { "address_spaces": { "M_AXI": { "range": "4G", "width": "32", "segments": { "SEG_processing_system7_0_HP0_DDR_LOWOCM": { "address_block": "/processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM", "offset": "0x00000000", "range": "1G" } } } } }, "/axi_cdma_0": { "address_spaces": { "Data": { "range": "4G", "width": "32", "segments": { "SEG_axi_pcie_0_BAR0": { "address_block": "/axi_pcie_0/S_AXI/BAR0", "offset": "0x40000000", "range": "256M" }, "SEG_axi_pcie_0_CTL0": { "address_block": "/axi_pcie_0/S_AXI_CTL/CTL0", "offset": "0x50000000", "range": "64M" }, "SEG_processing_system7_0_HP0_DDR_LOWOCM": { "address_block": "/processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM", "offset": "0x00000000", "range": "1G" }, "SEG_axi_cdma_0_Reg": { "address_block": "/axi_cdma_0/S_AXI_LITE/Reg", "offset": "0x7E200000", "range": "64K", "is_excluded": "TRUE" } } } } } } } }