//--------------------------------------------------------------------------------------------
//
// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
// ?? 3? 29 2020 15:44:24
//
//      Input file      : 
//      Component name  : multiplier
//      Author          : 
//      Company         : 
//
//      Description     : 
//
//
//--------------------------------------------------------------------------------------------


module multiplier(CLK, RESET, input1, input2, output_xhdl0);
   input        CLK;
   input        RESET;
   input [7:0]  input1;
   input [7:0]  input2;
   output [7:0] output_xhdl0;
   reg [7:0]    output_xhdl0;
   
   
   reg [15:0]   out_temp;
   reg [15:0]   input1_buf;
   reg [15:0]   part0;
   reg [15:0]   part1;
   reg [15:0]   part2;
   reg [15:0]   part3;
   reg [15:0]   part4;
   reg [15:0]   part5;
   reg [15:0]   part6;
   reg [15:0]   part7;
   
   
   always @(posedge CLK or posedge RESET)
      if (RESET == 1'b1)
      begin
         out_temp <= {16{1'b0}};
         output_xhdl0 <= {8{1'b0}};
         input1_buf <= {16{1'b0}};
         part0 <= {16{1'b0}};
         part1 <= {16{1'b0}};
         part2 <= {16{1'b0}};
         part3 <= {16{1'b0}};
         part4 <= {16{1'b0}};
         part5 <= {16{1'b0}};
         part6 <= {16{1'b0}};
         part7 <= {16{1'b0}};
      end
      else 
      begin
         input1_buf <= {input1[7], input1[7], input1[7], input1[7], input1[7], input1[7], input1[7], input1[7], signed_xhdl1(input1)};
         if (input2[0] == 1'b1)
            part0 <= -(input1_buf);
         else
            part0 <= {16{1'b0}};
         if (input2[1] == 1'b1)
         begin
            if (input2[0] == 1'b1)
               part1 <= {16{1'b0}};
            else
               part1 <= -(input1_buf);
         end
         else
            if (input2[0] == 1'b1)
               part1 <= input1_buf;
            else
               part1 <= {16{1'b0}};
         if (input2[2] == 1'b1)
         begin
            if (input2[1] == 1'b1)
               part2 <= {16{1'b0}};
            else
               part2 <= -(input1_buf);
         end
         else
            if (input2[1] == 1'b1)
               part2 <= input1_buf;
            else
               part2 <= {16{1'b0}};
         if (input2[3] == 1'b1)
         begin
            if (input2[2] == 1'b1)
               part3 <= {16{1'b0}};
            else
               part3 <= -(input1_buf);
         end
         else
            if (input2[2] == 1'b1)
               part3 <= input1_buf;
            else
               part3 <= {16{1'b0}};
         if (input2[4] == 1'b1)
         begin
            if (input2[3] == 1'b1)
               part4 <= {16{1'b0}};
            else
               part4 <= -(input1_buf);
         end
         else
            if (input2[3] == 1'b1)
               part4 <= input1_buf;
            else
               part4 <= {16{1'b0}};
         if (input2[5] == 1'b1)
         begin
            if (input2[4] == 1'b1)
               part5 <= {16{1'b0}};
            else
               part5 <= -(input1_buf);
         end
         else
            if (input2[4] == 1'b1)
               part5 <= input1_buf;
            else
               part5 <= {16{1'b0}};
         if (input2[6] == 1'b1)
         begin
            if (input2[5] == 1'b1)
               part6 <= {16{1'b0}};
            else
               part6 <= -(input1_buf);
         end
         else
            if (input2[5] == 1'b1)
               part6 <= input1_buf;
            else
               part6 <= {16{1'b0}};
         if (input2[7] == 1'b1)
         begin
            if (input2[6] == 1'b1)
               part7 <= {16{1'b0}};
            else
               part7 <= -(input1_buf);
         end
         else
            if (input2[6] == 1'b1)
               part7 <= input1_buf;
            else
               part7 <= {16{1'b0}};
         out_temp <= part0 + ({part1[14:0], 1'b0}) + ({part2[13:0], 2'b00}) + ({part3[12:0], 3'b000}) + ({part4[11:0], 4'b0000}) + ({part5[10:0], 5'b00000}) + ({part6[9:0], 6'b000000}) + ({part7[8:0], 7'b0000000});
         output_xhdl0 <= out_temp[15:8];
      end
   
endmodule