454 lines
14 KiB
VHDL
454 lines
14 KiB
VHDL
-------------------------------------------------------------------------------
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-- Copyright (c) 1995/2015 Xilinx, Inc.
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-- All Right Reserved.
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-------------------------------------------------------------------------------
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-- ____ ____
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-- / /\/ /
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-- /___/ \ / Vendor : Xilinx
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-- \ \ \/ Version : 2015.3
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-- \ \ Description : Xilinx Functional Simulation Library Component
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-- / / Macro for DSP48
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-- /___/ /\ Filename : ADDMACC_MACRO.vhd
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-- \ \ / \
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-- \___\/\___\
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--
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-- Revision:
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-- 04/18/08 - Initial version.
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-- 04/09/15 - 852167 - align with verilog
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-- End Revision
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----- CELL ADDMACC_MACRO -----
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library IEEE;
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use ieee.std_logic_1164.ALL;
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use ieee.numeric_std.ALL;
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use IEEE.std_logic_arith.all;
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use IEEE.std_logic_unsigned.all;
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library UNISIM;
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use UNISIM.vcomponents.all;
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library STD;
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use STD.TEXTIO.ALL;
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entity ADDMACC_MACRO is
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generic (
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DEVICE : string := "VIRTEX6";
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LATENCY : integer := 4;
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WIDTH_PREADD : integer := 25;
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WIDTH_MULTIPLIER : integer := 18;
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WIDTH_PRODUCT : integer := 48
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);
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port (
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PRODUCT : out std_logic_vector(WIDTH_PRODUCT-1 downto 0);
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CARRYIN : in std_logic;
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CE : in std_logic;
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CLK : in std_logic;
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MULTIPLIER : in std_logic_vector(WIDTH_MULTIPLIER-1 downto 0);
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LOAD : in std_logic;
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LOAD_DATA : in std_logic_vector(WIDTH_PRODUCT-1 downto 0);
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PREADD1 : in std_logic_vector(WIDTH_PREADD-1 downto 0);
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PREADD2 : in std_logic_vector(WIDTH_PREADD-1 downto 0);
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RST : in std_logic
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);
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end entity ADDMACC_MACRO;
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architecture addmacc of ADDMACC_MACRO is
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function CheckDevice (
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device : in string
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) return boolean is
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variable func_val : boolean;
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variable Message : LINE;
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begin
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if (DEVICE = "VIRTEX6" or DEVICE = "SPARTAN6" or DEVICE = "7SERIES") then
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func_val := true;
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else
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func_val := false;
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write( Message, STRING'("Illegal value of Attribute DEVICE : ") );
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write ( Message, DEVICE);
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write( Message, STRING'(". Legal values of this attribute are ") );
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write( Message, STRING'(" VIRTEX6, SPARTAN6, 7SERIES. ") );
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ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
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DEALLOCATE (Message);
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end if;
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return func_val;
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end;
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function CheckWidthPreadd (
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width : in integer;
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device : in string
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) return boolean is
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variable func_val : boolean;
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variable Message : LINE;
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begin
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if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then
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if (width > 0 and width <= 25) then
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func_val := true;
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else
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func_val := false;
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write( Message, STRING'("Illegal value of Attribute WIDTH_PREADD : ") );
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write ( Message, WIDTH_PREADD);
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write( Message, STRING'(". Legal values of this attribute are ") );
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write( Message, STRING'(" 1 to 25 ") );
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ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
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DEALLOCATE (Message);
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end if;
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-- begin s1
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else
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if (DEVICE = "SPARTAN6" and width > 0 and width <= 18) then
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func_val := true;
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else
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func_val := false;
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write( Message, STRING'("Illegal value of Attribute WIDTH_PREADD : ") );
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write ( Message, WIDTH_PREADD);
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write( Message, STRING'(". Legal values of this attribute are ") );
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write( Message, STRING'(" 1 to 18 ") );
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ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
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DEALLOCATE (Message);
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end if;
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-- end s1
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end if;
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return func_val;
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end;
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function GetWidthPreadd (
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device : in string
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) return integer is
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variable func_val : integer;
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variable Message : LINE;
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begin
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if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then
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func_val := 25;
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else
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func_val := 18;
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DEALLOCATE (Message);
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end if;
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return func_val;
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end;
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function CheckWidthMult (
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width : in integer
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) return boolean is
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variable func_val : boolean;
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variable Message : LINE;
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begin
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if (width > 0 and width <= 18 ) then
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func_val := true;
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else
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func_val := false;
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write( Message, STRING'("Illegal value of Attribute WIDTH_MULTPLIER : ") );
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write ( Message, WIDTH_MULTIPLIER);
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write( Message, STRING'(". Legal values of this attribute are ") );
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write( Message, STRING'(" 1 to 18 ") );
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ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
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DEALLOCATE (Message);
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end if;
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return func_val;
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end;
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function CheckWidthProd (
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width : in integer
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) return boolean is
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variable func_val : boolean;
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variable Message : LINE;
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begin
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if (width > 0 and width <= 48 ) then
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func_val := true;
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else
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func_val := false;
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write( Message, STRING'("Illegal value of Attribute WIDTH_PRODUCT : ") );
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write ( Message, WIDTH_PRODUCT);
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write( Message, STRING'(". Legal values of this attribute are ") );
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write( Message, STRING'(" 1 to 48 ") );
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ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
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DEALLOCATE (Message);
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end if;
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return func_val;
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end;
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function GetABREG_IN (
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latency : in integer
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) return integer is
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variable func_width : integer;
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begin
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if (LATENCY = 2 or LATENCY = 3) then
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func_width := 1;
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elsif (LATENCY = 4 ) then
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func_width := 2;
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else
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func_width := 0;
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end if;
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return func_width;
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end;
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function GetABREG1_IN (
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latency : in integer
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) return integer is
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variable func_width : integer;
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begin
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if (LATENCY = 2 or LATENCY = 3 or LATENCY = 4) then
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func_width := 1;
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else
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func_width := 0;
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end if;
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return func_width;
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end;
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function GetABREG0_IN (
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latency : in integer
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) return integer is
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variable func_width : integer;
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begin
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if (LATENCY = 4) then
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func_width := 1;
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else
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func_width := 0;
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end if;
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return func_width;
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end;
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function GetMREG_IN (
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latency : in integer
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) return integer is
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variable func_width : integer;
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begin
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if (LATENCY = 3 or LATENCY = 4 ) then
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func_width := 1;
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else
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func_width := 0;
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end if;
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return func_width;
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end;
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function GetPREG_IN (
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latency : in integer
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) return integer is
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variable func_width : integer;
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variable Message : LINE;
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begin
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if (LATENCY = 1 or LATENCY = 2 or LATENCY = 3 or LATENCY = 4 ) then
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func_width := 1;
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else
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func_width := 0;
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write( Message, STRING'("Illegal value of Attribute LATENCY : ") );
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write ( Message, LATENCY);
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write( Message, STRING'(". Legal values of this attribute are ") );
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write( Message, STRING'(" 1 to 4 ") );
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ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
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DEALLOCATE (Message);
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end if;
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return func_width;
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end;
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function GetOPMODE_IN (
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device : in string
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) return integer is
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variable func_width : integer;
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begin
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if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then
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func_width := 7;
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elsif (DEVICE = "SPARTAN6") then
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func_width := 8;
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else
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func_width := 8;
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end if;
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return func_width;
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end;
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--Signal Declarations:
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constant OPMODE_WIDTH : integer := GetOPMODE_IN(DEVICE);
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constant ChkDevice : boolean := CheckDevice(DEVICE);
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constant ChkWidthPreAdd : boolean := CheckWidthPreAdd(WIDTH_PREADD, DEVICE);
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constant MaxWidthPreAdd : integer := GetWidthPreAdd(DEVICE);
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constant ChkWidthMult : boolean := CheckWidthMult(WIDTH_MULTIPLIER);
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constant ChkWidthProd : boolean := CheckWidthProd(WIDTH_PRODUCT);
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constant AREG_IN : integer := GetABREG_IN(LATENCY);
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constant BREG_IN : integer := GetABREG_IN(LATENCY);
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constant A0REG_IN : integer := GetABREG0_IN(LATENCY);
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constant B0REG_IN : integer := GetABREG0_IN(LATENCY);
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constant A1REG_IN : integer := GetABREG1_IN(LATENCY);
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constant B1REG_IN : integer := GetABREG1_IN(LATENCY);
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constant MREG_IN : integer := GetMREG_IN(LATENCY);
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constant PREG_IN : integer := GetPREG_IN(LATENCY);
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signal OPMODE_IN : std_logic_vector((OPMODE_WIDTH-1) downto 0);
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signal PREADD1_IN : std_logic_vector(29 downto 0) := "000000000000000000000000000000";
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signal PREADD2_IN : std_logic_vector(24 downto 0) := "0000000000000000000000000";
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signal MULTIPLIER_IN : std_logic_vector(17 downto 0) := "000000000000000000";
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signal LOAD_DATA_IN : std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000";
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signal RESULT_OUT : std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000";
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signal CEA1_IN : std_logic;
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signal CEA2_IN : std_logic;
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signal CEB1_IN : std_logic;
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signal CEB2_IN : std_logic;
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-- Architecture Section: instantiation
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begin
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CEA1_IN <= CE when (AREG_IN = 2) else '0';
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CEA2_IN <= CE when (AREG_IN = 1 or AREG_IN = 2) else '0';
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CEB1_IN <= CE when (BREG_IN = 2) else '0';
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CEB2_IN <= CE when (BREG_IN = 1 or BREG_IN = 2) else '0';
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v : if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate
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OPMODE_IN <= "01" & LOAD & "0101";
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end generate v;
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s : if (DEVICE = "SPARTAN6") generate
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OPMODE_IN <= "00011" & LOAD & "01";
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end generate s;
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load1 : if (WIDTH_PRODUCT = 48) generate
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begin
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LOAD_DATA_IN <= LOAD_DATA;
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end generate load1;
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load2 : if (WIDTH_PRODUCT < 48) generate
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begin
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l1: for i in 47 downto WIDTH_PRODUCT generate
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LOAD_DATA_IN(i) <= '0';
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end generate;
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LOAD_DATA_IN(WIDTH_PRODUCT-1 downto 0) <= LOAD_DATA;
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end generate load2;
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pa1 : if (WIDTH_PREADD = MaxWidthPreAdd) generate
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begin
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PREADD1_IN(MaxWidthPreAdd-1 downto 0) <= PREADD1;
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PREADD2_IN(MaxWidthPreAdd-1 downto 0) <= PREADD2;
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end generate pa1;
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mult1 : if (WIDTH_MULTIPLIER = 18) generate
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begin
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MULTIPLIER_IN <= MULTIPLIER;
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end generate mult1;
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pa2 : if (WIDTH_PREADD < MaxWidthPreAdd) generate
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begin
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pa: for i in MaxWidthPreAdd-1 downto WIDTH_PREADD generate
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PREADD1_IN(i) <= PREADD1((WIDTH_PREADD-1));
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PREADD2_IN(i) <= PREADD2((WIDTH_PREADD-1));
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end generate;
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PREADD1_IN(WIDTH_PREADD-1 downto 0) <= PREADD1;
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PREADD2_IN(WIDTH_PREADD-1 downto 0) <= PREADD2;
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end generate pa2;
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mult2 : if (WIDTH_MULTIPLIER < 18) generate
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begin
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m1: for i in 17 downto WIDTH_MULTIPLIER generate
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MULTIPLIER_IN(i) <= MULTIPLIER((WIDTH_MULTIPLIER-1));
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end generate;
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MULTIPLIER_IN(WIDTH_MULTIPLIER-1 downto 0) <= MULTIPLIER;
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end generate mult2;
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PRODUCT <= RESULT_OUT(WIDTH_PRODUCT-1 downto 0);
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-- begin generate virtex6
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bl : if (DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate
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begin
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DSP48E_1: DSP48E1
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generic map (
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ACASCREG => AREG_IN,
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AREG => AREG_IN,
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BCASCREG => BREG_IN,
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BREG => BREG_IN,
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MREG => MREG_IN,
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PREG => PREG_IN,
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USE_DPORT => TRUE)
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port map (
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ACOUT => open,
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BCOUT => open,
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CARRYCASCOUT => open,
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CARRYOUT => open,
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MULTSIGNOUT => open,
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OVERFLOW => open,
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P => RESULT_OUT,
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PATTERNBDETECT => open,
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PATTERNDETECT => open,
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PCOUT => open,
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UNDERFLOW => open,
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A => PREADD1_IN,
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ACIN => "000000000000000000000000000000",
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ALUMODE => "0000",
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B => MULTIPLIER_IN,
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BCIN => "000000000000000000",
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C => LOAD_DATA_IN,
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CARRYCASCIN => '0',
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CARRYIN => CARRYIN,
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CARRYINSEL => "000",
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CEA1 => CEA1_IN,
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CEA2 => CEA2_IN,
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CEAD => CE,
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CEALUMODE => CE,
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CEB1 => CEB1_IN,
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CEB2 => CEB2_IN,
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CEC => CE,
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CECARRYIN => CE,
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CECTRL => CE,
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CED => CE,
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CEINMODE => CE,
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CEM => CE,
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CEP => CE,
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CLK => CLK,
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D => PREADD2_IN,
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INMODE => "00100",
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MULTSIGNIN => '0',
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OPMODE => OPMODE_IN,
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PCIN => "000000000000000000000000000000000000000000000000",
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RSTA => RST,
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RSTALLCARRYIN => RST,
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RSTALUMODE => RST,
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RSTB => RST,
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RSTC => RST,
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RSTCTRL => RST,
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RSTD => RST,
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RSTINMODE => RST,
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RSTM => RST,
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RSTP => RST
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);
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end generate bl;
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-- end generate virtex6
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-- begin generate spartan6
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st : if DEVICE = "SPARTAN6" generate
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begin
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DSP48E_2: DSP48A1
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generic map (
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A0REG => A0REG_IN,
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A1REG => A1REG_IN,
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B0REG => B0REG_IN,
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B1REG => B1REG_IN,
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MREG => MREG_IN,
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PREG => PREG_IN )
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port map (
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BCOUT => open,
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CARRYOUT => open,
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CARRYOUTF => open,
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M => open,
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P => RESULT_OUT,
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PCOUT => open,
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A => MULTIPLIER_IN,
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B => PREADD1_IN(17 downto 0),
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C => LOAD_DATA_IN,
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CARRYIN => CARRYIN,
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CEA => CE,
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CEB => CE,
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CEC => CE,
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CECARRYIN => '0',
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CED => CE,
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CEM => CE,
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CEOPMODE => CE,
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CEP => CE,
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CLK => CLK,
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D => PREADD2_IN(17 downto 0),
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OPMODE => OPMODE_IN,
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PCIN => "000000000000000000000000000000000000000000000000",
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RSTA => RST,
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RSTB => RST,
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RSTC => RST,
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RSTCARRYIN => RST,
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RSTD => RST,
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RSTM => RST,
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RSTOPMODE => RST,
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RSTP => RST
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);
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end generate st;
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-- end generate spartan6
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end addmacc;
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