148 lines
3.8 KiB
JSON
148 lines
3.8 KiB
JSON
{
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"apro": {
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"prefix": "apro",
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"body": "\n${1:identifier} : process( ${2:clock}, ${3:reset} )\nbegin\n if( ${3:reset} = '1' ) then\n $0\n elsif( rising_edge(${2:clock}) ) then\n\n end if ;\nend process ; -- ${1:identifier}\n",
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"description": "asynchronous process",
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"scope": "source.vhdl"
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},
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"arch": {
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"prefix": "arch",
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"body": "architecture ${1:arch} of ${2:ent} is\n\n\tsignal $0\n\nbegin\n\nend ${1:arch} ; -- ${1:arch}",
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"description": "architecture",
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"scope": "source.vhdl"
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},
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"case": {
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"prefix": "case",
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"body": "case( ${1:signal_name} ) is\n\n\twhen ${2:IDLE} =>\n\t\t$0\n\n\twhen others =>\n\nend case ;",
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"description": "case",
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"scope": "source.vhdl"
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},
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"else": {
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"prefix": "else",
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"body": "else\n\t$0",
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"description": "else",
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"scope": "source.vhdl"
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},
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"elsif": {
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"prefix": "elsif",
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"body": "elsif ${1:expression} then\n\t$0",
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"description": "elsif",
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"scope": "source.vhdl"
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},
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"ent": {
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"prefix": "ent",
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"body": "entity ${1:ent} is\n port (\n\t${0:clock}\n ) ;\nend ${1:ent};",
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"description": "entity",
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"scope": "source.vhdl"
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},
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"entarch": {
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"prefix": "entarch",
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"body": "entity ${1:ent} is\n port (\n\t${0:clock}\n ) ;\nend ${1:ent} ;\n\narchitecture ${2:arch} of ${1:ent} is\n\n\n\nbegin\n\n\n\nend architecture ; -- ${2:arch}",
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"description": "entity architecture",
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"scope": "source.vhdl"
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},
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"for": {
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"prefix": "for",
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"body": "${1:identifier} : for ${2:i} in ${3:0} to ${4:10} loop\n\t$0\nend loop ; -- ${1:identifier}",
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"description": "for loop",
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"scope": "source.vhdl"
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},
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"forg": {
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"prefix": "forg",
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"body": "${1:identifier} : for ${2:i} in ${3:x} to ${4:y} generate\n\t$0\nend generate ; -- ${1:identifier}",
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"description": "for generate",
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"scope": "source.vhdl"
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},
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"if": {
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"prefix": "if",
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"body": "if ${1:expression} then\n\t$0\nend if ;",
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"description": "if",
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"scope": "source.vhdl"
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},
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"pack": {
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"prefix": "pack",
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"body": "package ${1:pkg} is\n\t$0\nend package ;",
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"description": "package",
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"scope": "source.vhdl"
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},
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"pro": {
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"prefix": "pro",
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"body": "${1:identifier} : process( ${2:sensitivity_list} )\nbegin\n\t$0\nend process ; -- ${1:identifier}",
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"description": "process",
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"scope": "source.vhdl"
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},
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"s": {
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"prefix": "s",
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"body": "signed(${1:x} downto ${2:0}) ;$0",
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"description": "signed downto",
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"scope": "source.vhdl"
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},
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"sr": {
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"prefix": "sr",
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"body": "signed(${1:signal}'range) ;$0",
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"description": "signed range",
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"scope": "source.vhdl"
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},
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"spro": {
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"prefix": "spro",
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"body": "${1:identifier} : process( ${2:clock} )\nbegin\n\tif( rising_edge(${2:clock}) ) then\n\t\t$0\n\tend if ;\nend process ; -- ${1:identifier}",
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"description": "synchronous process",
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"scope": "source.vhdl"
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},
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"slv": {
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"prefix": "slv",
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"body": "std_logic_vector(${1:x} downto ${2:0}) ;$0",
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"description": "std_logic_vector downto",
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"scope": "source.vhdl"
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},
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"slvr": {
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"prefix": "slvr",
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"body": "std_logic_vector(${1:signal}'range) ;$0",
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"description": "std_logic_vector range",
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"scope": "source.vhdl"
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},
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"u": {
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"prefix": "u",
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"body": "unsigned(${1:x} downto ${2:0}) ;$0",
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"description": "unsigned downto",
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"scope": "source.vhdl"
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},
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"ur": {
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"prefix": "ur",
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"body": "unsigned(${1:signal}'range) ;$0",
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"description": "unsigned range",
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"scope": "source.vhdl"
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},
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"vhdl": {
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"prefix": "vhdl",
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"body": "library ieee ;\n\tuse ieee.std_logic_1164.all ;\n\tuse ieee.numeric_std.all ;\n\nentity ${1:ent} is\n port (\n\t${0:clock}\n ) ;\nend ${1:ent} ; \n\narchitecture ${2:arch} of ${1:ent} is\n\nbegin\n\nend architecture ;",
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"description": "vhdl template",
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"scope": "source.vhdl"
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},
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"while": {
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"prefix": "while",
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"body": "${1:identifier} : while ${2:expression} loop\n\t$0\nend loop ; -- ${1:identifier}",
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"description": "while",
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"scope": "source.vhdl"
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}
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} |