70 lines
2.1 KiB
Verilog
70 lines
2.1 KiB
Verilog
`timescale 1ns / 1ps
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module Image_XYCrop(
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input clk,
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input rst_n,
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//CMOS
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input image_in_vsync,
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input image_in_href,
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input image_in_data,
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output image_out_vsync,
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output image_out_href_left,
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output image_out_data_left,
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output image_out_href_right,
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output image_out_data_right
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);
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//-----------------------------------
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reg image_in_href_r = 0;
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reg image_in_vsync_r = 0;
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reg image_in_data_r = 0;
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always@(posedge clk or negedge rst_n) begin
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if(!rst_n) begin
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image_in_vsync_r <= 0;
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image_in_href_r <= 0;
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image_in_data_r <= 0;
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end
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else begin
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image_in_vsync_r <= image_in_vsync;
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image_in_href_r <= image_in_href;
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image_in_data_r <= image_in_data;
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end
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end
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//-----------------------------------
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//Image Ysize Crop
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reg [11:0] image_ypos = 0;
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wire image_in_href_negedge = (image_in_href_r & ~image_in_href) ? 1'b1 : 1'b0;
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always@(posedge clk or negedge rst_n) begin
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if(!rst_n)
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image_ypos <= 0;
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else if(image_in_vsync == 1'b1) begin
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if(image_in_href_negedge == 1'b1) //行同步信号的下降沿，一行信号赋值完成后，image_ypos累加1
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image_ypos <= image_ypos + 1'b1;
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else
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image_ypos <= image_ypos;
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end
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else
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image_ypos <= 0;
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end
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assign image_out_vsync = image_in_vsync_r; // image_out_vsync是打一拍后的 image_in_vsync的信号，延时了一个时钟周期
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//-----------------------------------
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//Image Hsize Crop
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reg [11:0] image_xpos = 0;
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always@(posedge clk or negedge rst_n) begin
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if(!rst_n)
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image_xpos <= 0;
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else if(image_in_href == 1'b1)
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image_xpos <= image_xpos + 1'b1;
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else
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image_xpos <= 0;
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end
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assign image_out_href_right = ((image_in_href_r == 1'b1) && (image_xpos > 10'd640) && (image_xpos < 12'd1280)) ? 1'b1 : 1'b0;
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assign image_out_data_right = (image_out_vsync & image_out_href_right) ? image_in_data_r : 1'd0;
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assign image_out_href_left = ((image_in_href_r == 1'b1) && (image_xpos <= 10'd640)) ? 1'b1 : 1'b0;
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assign image_out_data_left = (image_out_vsync & image_out_href_left) ? image_in_data_r : 1'd0;
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endmodule
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