163 lines
5.6 KiB
Verilog
163 lines
5.6 KiB
Verilog
`timescale 1ns/1ns
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module RAW8_RGB888 #(
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parameter [10:0] IMG_HDISP = 11'd640, //640*480
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parameter [10:0] IMG_VDISP = 11'd480
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) (
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//global clock
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input clk, //cmos video pixel clock
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input rst_n, //global reset
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//CMOS YCbCr444 data output
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input per_frame_vsync, //Prepared Image data vsync valid signal
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input per_frame_href, //Prepared Image data href vaild signal
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input [7:0] per_img_RAW, //Prepared Image data 8 Bit RAW Data
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//CMOS RGB888 data output
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output post_frame_vsync, //Processed Image data vsync valid signal
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output post_frame_href, //Processed Image data href vaild signal
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output [7:0] post_img_red, //Prepared Image green data to be processed
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output [7:0] post_img_green, //Prepared Image green data to be processed
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output [7:0] post_img_blue //Prepared Image blue data to be processed
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);
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//----------------------------------------------------
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//Generate 8Bit 3X3 Matrix for Video Image Processor.
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//Image data has been processd
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wire matrix_frame_vsync; //Prepared Image data vsync valid signal
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wire matrix_frame_href; //Prepared Image data href vaild signal
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wire [7:0] matrix_p11, matrix_p12, matrix_p13; //3X3 Matrix output
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wire [7:0] matrix_p21, matrix_p22, matrix_p23;
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wire [7:0] matrix_p31, matrix_p32, matrix_p33;
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Matrix_Generate_3X3_Buf # (
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.DATA_WIDTH ( 8 ),
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.IMG_HDISP (IMG_HDISP), //640*480
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.IMG_VDISP (IMG_VDISP)
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) Matrix_Generate_3X3_Buf_u (
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//global clock
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.clk (clk), //cmos video pixel clock
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.rst_n (rst_n), //global reset
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//Image data prepred to be processd
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.per_frame_vsync (per_frame_vsync), //Prepared Image data vsync valid signal
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.per_frame_href (per_frame_href), //Prepared Image data href vaild signal
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.per_img_Data (per_img_RAW), //Prepared Image brightness input
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//Image data has been processd
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.matrix_frame_vsync (matrix_frame_vsync), //Processed Image data vsync valid signal
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.matrix_frame_href (matrix_frame_href), //Processed Image data href vaild signal
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.matrix_p11(matrix_p11), .matrix_p12(matrix_p12), .matrix_p13(matrix_p13), //3X3 Matrix output
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.matrix_p21(matrix_p21), .matrix_p22(matrix_p22), .matrix_p23(matrix_p23),
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.matrix_p31(matrix_p31), .matrix_p32(matrix_p32), .matrix_p33(matrix_p33)
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);
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//-------------------------------------------------------------
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//sync the frame vsync and href signal and generate frame begin & end signal
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reg matrix_frame_href_r;
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always@(posedge clk or negedge rst_n) begin
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if(!rst_n)
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matrix_frame_href_r <= 0;
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else
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matrix_frame_href_r <= matrix_frame_href;
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end
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wire matrix_frame_href_end = (matrix_frame_href_r & ~matrix_frame_href) ? 1'b1 : 1'b0; //Line over signal
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//----------------------------------------
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//Count the frame lines
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reg [10:0] line_cnt;
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always@(posedge clk or negedge rst_n) begin
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if(!rst_n)
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line_cnt <= 0;
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else if(matrix_frame_vsync == 1'b1) begin
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if(matrix_frame_href_end)
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line_cnt <= (line_cnt < IMG_VDISP - 1'b1) ? line_cnt + 1'b1 : 10'd0;
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else
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line_cnt <= line_cnt;
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end
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else
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line_cnt <= 0;
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end
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//----------------------------------------
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//Count the pixels
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reg [10:0] point_cnt;
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always@(posedge clk or negedge rst_n) begin
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if(!rst_n)
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point_cnt <= 0;
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else if(matrix_frame_href == 1'b1) //Line valid
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point_cnt <= (line_cnt < IMG_HDISP - 1'b1) ? point_cnt + 1'b1 : 10'd0;
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else
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point_cnt <= 0;
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end
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//--------------------------------------
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//Convet RAW 2 RGB888 Format
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//
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localparam OddLINE_OddPOINT = 2'b10; //odd lines + odd point
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localparam OddLINE_Even_POINT = 2'b11; //odd lines + even point
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localparam EvenLINE_OddPOINT = 2'b00; //even lines + odd point
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localparam EvenLINE_EvenPOINT = 2'b01; //even lines + even point
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reg [9:0] post_img_red_r;
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reg [9:0] post_img_green_r;
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reg [9:0] post_img_blue_r;
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always@(posedge clk or negedge rst_n) begin
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if(!rst_n) begin
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post_img_red_r <= 0;
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post_img_green_r<= 0;
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post_img_blue_r <= 0;
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end
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else begin
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case({line_cnt[0], point_cnt[0]})
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//-------------------------BGBG...BGBG--------------------//
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OddLINE_OddPOINT:begin //odd lines + odd point
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//Center Blue
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post_img_red_r <= (matrix_p11 + matrix_p13 + matrix_p31 + matrix_p33)>>2;
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post_img_green_r<= (matrix_p12 + matrix_p21 + matrix_p23 + matrix_p32)>>2;
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post_img_blue_r <= matrix_p22;
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end
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OddLINE_Even_POINT:begin //odd lines + even point
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//Center Green
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post_img_red_r <= (matrix_p12 + matrix_p32)>>1;
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post_img_green_r<= matrix_p22;
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post_img_blue_r <= (matrix_p21 + matrix_p23)>>1;
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end
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//-------------------------GRGR...GRGR--------------------//
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EvenLINE_OddPOINT:begin //even lines + odd point
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//Center Green
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post_img_red_r <= (matrix_p21 + matrix_p23)>>1;
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post_img_green_r<= matrix_p22;
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post_img_blue_r <= (matrix_p12 + matrix_p32)>>1;
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end
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EvenLINE_EvenPOINT:begin //even lines + even point
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//Center Red
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post_img_red_r <= matrix_p22;
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post_img_green_r<= (matrix_p12 + matrix_p21 + matrix_p23 + matrix_p32)>>2;
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post_img_blue_r <= (matrix_p11 + matrix_p13 + matrix_p31 + matrix_p33)>>2;
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end
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endcase
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end
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end
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assign post_img_red = post_img_red_r[7:0];
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assign post_img_green = post_img_green_r[7:0];
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assign post_img_blue = post_img_blue_r[7:0];
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//------------------------------------------
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//lag n clocks signal sync
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reg [1:0] post_frame_vsync_r;
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reg [1:0] post_frame_href_r;
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always@(posedge clk or negedge rst_n) begin
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if(!rst_n) begin
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post_frame_vsync_r <= 0;
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post_frame_href_r <= 0;
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end
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else begin
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post_frame_vsync_r <= {post_frame_vsync_r[0], matrix_frame_vsync};
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post_frame_href_r <= {post_frame_href_r[0], matrix_frame_href};
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end
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end
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assign post_frame_vsync = post_frame_vsync_r[0];
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assign post_frame_href = post_frame_href_r[0];
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endmodule
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