38 lines
802 B
Verilog
38 lines
802 B
Verilog
module AD9226_driver #
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(
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parameter signed CH_offset = 27
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)
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(
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input clk_in,
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input rst_n,
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input [11:0] AD_data,
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output AD_clk,
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output [11:0] wave_CH
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);
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reg signed [11:0] wave_CH_buf;
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always@(posedge clk_in or negedge rst_n) begin
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if(!rst_n)
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wave_CH_buf <= 12'd0;
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else begin
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wave_CH_buf[11] <= AD_data[0];
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wave_CH_buf[10] <= AD_data[1];
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wave_CH_buf[9] <= AD_data[2];
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wave_CH_buf[8] <= AD_data[3];
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wave_CH_buf[7] <= AD_data[4];
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wave_CH_buf[6] <= AD_data[5];
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wave_CH_buf[5] <= AD_data[6];
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wave_CH_buf[4] <= AD_data[7];
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wave_CH_buf[3] <= AD_data[8];
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wave_CH_buf[2] <= AD_data[9];
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wave_CH_buf[1] <= AD_data[10];
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wave_CH_buf[0] <= AD_data[11];
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end
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end
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assign wave_CH = $signed(wave_CH_buf) + $signed(CH_offset);
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assign AD_clk = clk_in;
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endmodule
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