66 lines
2.1 KiB
Verilog
66 lines
2.1 KiB
Verilog
`timescale 1ns / 1ps
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module DAC3162_driver (
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input clk_in,
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input clk_div,
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input [11:0] DA3162_CH1,
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input [11:0] DA3162_CH2,
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/*DAC*/
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output [11:0] dac_data_p,
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output [11:0] dac_data_n,
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output dac_clk_p,
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output dac_clk_n,
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output dac_sleep
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);
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assign dac_sleep = 1'd1;
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reg [11:0] dac_a_int = 0;
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reg [11:0] dac_b_int = 0;
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reg [11:0] dac_a_intt = 0;
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reg [11:0] dac_b_intt = 0;
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reg [1:0] cnt_clk = 0;
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reg [3:0] power_on_rst_cnt = 4'h0;
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reg power_on_rst = 1;
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always @ (posedge clk_in) begin
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dac_a_int<=DA3162_CH1 + 12'b100000000000;
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dac_b_int<=DA3162_CH2 + 12'b100000000000;
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dac_a_intt<=dac_a_int;
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dac_b_intt<=dac_b_int;
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end
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always @ (posedge clk_div) begin
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if (power_on_rst_cnt == 4'hf) begin
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power_on_rst_cnt <= power_on_rst_cnt;
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power_on_rst <= 0;
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end
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else begin
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power_on_rst_cnt <= power_on_rst_cnt + 1;
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power_on_rst <= 1;
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end
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end
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LVDS_DDR_clk DAC3162_clk_u (
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.data_out_from_device ( 4'b0101 ), // input [3:0] data_out_from_device
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.data_out_to_pins_p ( dac_clk_p ), // output [0:0] data_out_to_pins_p
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.data_out_to_pins_n ( dac_clk_n ), // output [0:0] data_out_to_pins_n
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.clk_in ( clk_in ), // input clk_in
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.clk_div_in ( clk_div ), // input clk_div_in
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.io_reset ( power_on_rst ) // input io_reset
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);
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// input [47:0] data_out_from_device
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LVDS_DDR_data DAC3162_data_u (
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.clk_in ( clk_in ), // input clk_in
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.clk_div_in ( clk_div ), // input clk_div_in
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.data_out_from_device ({dac_a_int,dac_b_int,dac_a_intt,dac_b_intt} ),
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.data_out_to_pins_p ( dac_data_p ), // output [11:0] data_out_to_pins_p
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.data_out_to_pins_n ( dac_data_n ), // output [11:0] data_out_to_pins_n
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.io_reset ( power_on_rst ) // input io_reset
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);
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endmodule
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