78 lines
1.5 KiB
Verilog
78 lines
1.5 KiB
Verilog
`timescale 1ns / 1ps
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module uart_rx(
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input clk_50m,
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input uart_rx,
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output [7:0] uart_rx_data,
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output uart_rx_done
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);
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parameter [12:0] BAUD_DIV = 13'd87;//bps115200 每位数据传输时间为t=1/115200 s,周期T=1/100000000，计数值为t/T=868
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parameter [12:0] BAUD_DIV_CAP = 13'd43;
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reg [12:0] baud_div=0;
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reg baud_bps=0;
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reg bps_start=0;
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always@(posedge clk_50m)
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begin
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if(baud_div==BAUD_DIV_CAP)
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begin
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baud_bps<=1'b1;
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baud_div<=baud_div+1'b1;
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end
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else if(baud_div<BAUD_DIV && bps_start)
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begin
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baud_div<=baud_div+1'b1;
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baud_bps<=0;
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end
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else
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begin
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baud_bps<=0;
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baud_div<=0;
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end
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end
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reg [4:0] uart_rx_r=5'b11111;
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always@(posedge clk_50m)
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begin
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uart_rx_r<={uart_rx_r[3:0],uart_rx};
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end
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wire uart_rxnt=uart_rx_r[4]|uart_rx_r[3]|uart_rx_r[2]|uart_rx_r[1]|uart_rx_r[0];
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reg [3:0] bit_num=0;
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reg state=1'b0;
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reg [7:0] uart_rx_data_r0=0;
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reg [7:0] uart_rx_data_r1=0;
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reg uart_rx_dong_r=0;
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always@(posedge clk_50m)
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begin
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uart_rx_dong_r <= 0;
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case(state)
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1'b0 :
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if(!uart_rxnt)
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begin
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bps_start<=1'b1;
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state<=1'b1;
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end
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1'b1 :
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if(baud_bps)
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begin
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bit_num<=bit_num+1'b1;
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if(bit_num<4'd9)
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uart_rx_data_r0[bit_num-1]<=uart_rx;
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end
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else if(bit_num==4'd10)
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begin
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bit_num<=0;
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uart_rx_dong_r <= 1;
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uart_rx_data_r1<=uart_rx_data_r0;
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state<=1'b0;
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bps_start<=0;
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end
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default:;
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endcase
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end
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assign uart_rx_data=uart_rx_data_r1;
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assign uart_rx_done= uart_rx_dong_r;
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endmodule |