61 lines
1.9 KiB
Verilog
61 lines
1.9 KiB
Verilog
module uart_rx_control
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(
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input clk_50m,
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input rst_n,
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input uart_rx_done,
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input [7:0] uart_rx_data,
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output [31:0] data_out_0,
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output [15:0] data_out_1,
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output [15:0] data_out_2,
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output uart_done
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);
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reg [31:0] uart_data_buf_0;
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reg [31:0] data_out_r_0;
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reg [15:0] uart_data_buf_1;
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reg [15:0] data_out_r_1;
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reg [15:0] uart_data_buf_2;
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reg [15:0] data_out_r_2;
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reg [4:0] state;
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reg uart_done_buf;
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always@(posedge clk_50m or negedge rst_n)
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begin
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if(!rst_n)
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begin
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state <= 4'd0;
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uart_data_buf_0 <= 32'd0;
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uart_data_buf_1 <= 15'd0;
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uart_data_buf_2 <= 15'd0;
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uart_done_buf <= 1'd0;
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end
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else
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begin
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case(state)
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5'd0:begin uart_done_buf<=1'd0; state<=state+1; end
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5'd1:if((uart_rx_data == 8'h99)&&uart_rx_done)begin state<=state+1; end
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5'd2:if((uart_rx_data == 8'h50)&&uart_rx_done)begin state<=state+1; end
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5'd3:if(uart_rx_done)begin uart_data_buf_0[7:0]<=uart_rx_data; state<=state+1; end
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5'd4:if(uart_rx_done)begin uart_data_buf_0[15:8]<=uart_rx_data; state<=state+1; end
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5'd5:if(uart_rx_done)begin uart_data_buf_0[23:16]<=uart_rx_data; state<=state+1; end
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5'd6:if(uart_rx_done)begin uart_data_buf_0[31:24]<=uart_rx_data; state<=state+1; end
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5'd7:if(uart_rx_done)begin uart_data_buf_1[7:0]<=uart_rx_data; state<=state+1; end
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5'd8:if(uart_rx_done)begin uart_data_buf_1[15:8]<=uart_rx_data; state<=state+1; end
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5'd9:if(uart_rx_done)begin uart_data_buf_2[7:0]<=uart_rx_data; state<=state+1; end
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5'd10:if(uart_rx_done)begin uart_data_buf_2[15:8]<=uart_rx_data; state<=state+1; end
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5'd11:begin data_out_r_0<=uart_data_buf_0;
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data_out_r_1<=uart_data_buf_1;
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data_out_r_2<=uart_data_buf_2;
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uart_done_buf<=1'd1; state<=4'd0;
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end
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endcase
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end
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end
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assign data_out_0 = data_out_r_0;
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assign data_out_1 = data_out_r_1;
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assign data_out_2 = data_out_r_2;
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assign uart_done = uart_done_buf;
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endmodule
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