46 lines
1.1 KiB
Verilog
46 lines
1.1 KiB
Verilog
`timescale 1ns/1ns
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module Sort3 (
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input clk,
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input rst_n,
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input [7:0] data1, data2, data3,
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output reg [7:0] max_data, mid_data, min_data
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);
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//-----------------------------------
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//Sort of 3 datas
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always@(posedge clk or negedge rst_n) begin
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if(!rst_n) begin
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max_data <= 0;
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mid_data <= 0;
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min_data <= 0;
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end
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else begin
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//get the max value
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if(data1 >= data2 && data1 >= data3)
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max_data <= data1;
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else if(data2 >= data1 && data2 >= data3)
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max_data <= data2;
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else//(data3 >= data1 && data3 >= data2)
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max_data <= data3;
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//get the mid value
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if((data1 >= data2 && data1 <= data3) || (data1 >= data3 && data1 <= data2))
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mid_data <= data1;
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else if((data2 >= data1 && data2 <= data3) || (data2 >= data3 && data2 <= data1))
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mid_data <= data2;
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else//((data3 >= data1 && data3 <= data2) || (data3 >= data2 && data3 <= data1))
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mid_data <= data3;
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//ge the min value
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if(data1 <= data2 && data1 <= data3)
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min_data <= data1;
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else if(data2 <= data1 && data2 <= data3)
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min_data <= data2;
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else//(data3 <= data1 && data3 <= data2)
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min_data <= data3;
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end
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end
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endmodule
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