63 lines
2.0 KiB
Verilog
63 lines
2.0 KiB
Verilog
module phase_acc(clr,en,rst,valid_out1,clk,add_sub,sel,D,Q);
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parameter DATASIZE=16;
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input clr,en,rst,clk,add_sub,sel,valid_out1;
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input [DATASIZE-1:0] D;
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output [DATASIZE:0] Q;
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reg count0,count1,count2,count3;
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reg [DATASIZE:0] b_tmp,b_tmp0,b_tmp1,b_tmp2;
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reg [3:0] sum0;
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reg [7:0] sum1;
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reg [11:0] sum2;
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reg [16:0] sum3;
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reg add_sub0,add_sub1,add_sub2;
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reg clr0,clr1,clr2;
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always @(posedge clk) begin
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case({clr,add_sub})
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2'b00:{count0,sum0}<={1'b0,sum0}+{1'b0,D[3:0]};
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2'b01:{count0,sum0}<={1'b0,sum0}-{1'b0,D[3:0]};
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2'b10:{count0,sum0}<=5'b0+{1'b0,D[3:0]};
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default:{count0,sum0}<=5'b0-{1'b0,D[3:0]};
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endcase
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b_tmp0<=D;
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clr0<=clr;
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add_sub0<=add_sub;
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end
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always @(posedge clk)
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begin
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case({clr0,add_sub0})
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2'b00:{count1,sum1}<={{1'b0,sum1[7:4]}+{1'b0,b_tmp0[7:4]}+count0,sum0};
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2'b01:{count1,sum1}<={{1'b0,sum1[7:4]}-{1'b0,b_tmp0[7:4]}-count0,sum0};
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2'b10:{count1,sum1}<=5'b0+{1'b0,b_tmp0[7:4]};
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default:{count1,sum1}<=5'b0-{1'b0,b_tmp0[7:4]};
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endcase
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b_tmp1<=b_tmp0;
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clr1<=clr0;
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add_sub1<=add_sub0;
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end
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always @(posedge clk)
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begin
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case({clr1,add_sub1})
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2'b00:{count2,sum2}<={{1'b0,sum2[11:8]}+{1'b0,b_tmp1[11:8]}+count1,sum1};
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2'b01:{count2,sum2}<={{1'b0,sum2[11:8]}-{1'b0,b_tmp1[11:8]}-count1,sum1};
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2'b10:{count2,sum2}<=5'b0+{1'b0,b_tmp1[11:8]};
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default:{count2,sum2}<=5'b0-{1'b0,b_tmp1[11:8]};
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endcase
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b_tmp2<=b_tmp1;
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clr2<=clr1;
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add_sub2<=add_sub1;
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end
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always @(posedge clk) begin
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case({clr2,add_sub2})
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2'b00:sum3<={sum3[16:12]+{1'b0,b_tmp2[15:12]}+count2,sum2};
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2'b01:sum3<={sum3[16:12]-{1'b0,b_tmp2[15:12]}-count2,sum2};
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2'b10:sum3<=5'b0+{1'b0,b_tmp2[15:12]};
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default:sum3<=5'b0-{1'b0,b_tmp2[15:12]};
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endcase
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end
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assign Q=sum3;
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endmodule |