300 lines
9.2 KiB
Verilog
300 lines
9.2 KiB
Verilog
`timescale 1 ns / 1 ps
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module AXI #(
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parameter integer OUTPUT_WIDTH = 12,
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parameter integer PHASE_WIDTH = 32,
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parameter integer C_S_AXI_DATA_WIDTH = 32,
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parameter integer C_S_AXI_ADDR_WIDTH = 4
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) (
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// Users to add ports here
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// User ports ends
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// Do not modify the ports beyond this line
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input wire S_AXI_ACLK,
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input wire S_AXI_ARESETN,
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input wire S_AXI_WVALID,
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output wire S_AXI_RVALID,
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output wire S_AXI_WREADY,
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input wire S_AXI_RREADY,
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input wire S_AXI_AWVALID,
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input wire S_AXI_ARVALID,
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output wire S_AXI_AWREADY,
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output wire S_AXI_ARREADY,
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input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
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input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
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input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
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output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
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input wire [2 : 0] S_AXI_AWPROT,
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input wire [2 : 0] S_AXI_ARPROT,
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output wire [1 : 0] S_AXI_BRESP,
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output wire [1 : 0] S_AXI_RRESP,
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output wire S_AXI_BVALID,
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input wire S_AXI_BREADY,
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input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB
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);
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// AXI4LITE signals
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reg axi_awready;
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reg axi_arready;
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reg axi_bvalid;
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reg axi_rvalid;
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reg axi_wready;
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reg [1 : 0] axi_bresp;
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reg [1 : 0] axi_rresp;
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reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
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reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
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reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata;
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// Example-specific design signals
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// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
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// ADDR_LSB is used for addressing 32/64 bit registers/memories
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// ADDR_LSB = 2 for 32 bits (n downto 2)
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// ADDR_LSB = 3 for 64 bits (n downto 3)
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localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
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localparam integer OPT_MEM_ADDR_BITS = 1;
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//----------------------------------------------
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//-- Signals for user logic register space example
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//------------------------------------------------
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//-- Number of Slave Registers 4
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reg aw_en;
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wire slv_reg_rden;
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wire slv_reg_wren;
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reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg0;
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reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg1;
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reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg2;
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reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg3;
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reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out;
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integer byte_index;
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// I/O Connections assignments
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assign S_AXI_AWREADY = axi_awready;
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assign S_AXI_WREADY = axi_wready;
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assign S_AXI_BRESP = axi_bresp;
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assign S_AXI_BVALID = axi_bvalid;
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assign S_AXI_ARREADY = axi_arready;
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assign S_AXI_RDATA = axi_rdata;
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assign S_AXI_RRESP = axi_rresp;
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assign S_AXI_RVALID = axi_rvalid;
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// Implement axi_awready generation
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// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
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// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
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// de-asserted when reset is low.
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always @( posedge S_AXI_ACLK ) begin
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if ( S_AXI_ARESETN == 1'b0 ) begin
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axi_awready <= 1'b0;
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aw_en <= 1'b1;
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end
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else begin
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if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en) begin
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axi_awready <= 1'b1;
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aw_en <= 1'b0;
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end
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else if (S_AXI_BREADY && axi_bvalid) begin
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aw_en <= 1'b1;
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axi_awready <= 1'b0;
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end
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else begin
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axi_awready <= 1'b0;
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end
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end
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end
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// Implement axi_awaddr latching
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// This process is used to latch the address when both
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// S_AXI_AWVALID and S_AXI_WVALID are valid.
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always @( posedge S_AXI_ACLK ) begin
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if ( S_AXI_ARESETN == 1'b0 ) begin
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axi_awaddr <= 0;
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end
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else begin
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if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en) begin
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// Write Address latching
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axi_awaddr <= S_AXI_AWADDR;
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end
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end
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end
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// Implement axi_wready generation
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// axi_wready is asserted for one S_AXI_ACLK clock cycle when both
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// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
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// de-asserted when reset is low.
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always @( posedge S_AXI_ACLK ) begin
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if ( S_AXI_ARESETN == 1'b0 ) begin
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axi_wready <= 1'b0;
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end
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else begin
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if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID && aw_en ) begin
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axi_wready <= 1'b1;
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end
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else begin
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axi_wready <= 1'b0;
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end
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end
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end
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// Implement write response logic generation
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// The write response and response valid signals are asserted by the slave
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// when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
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// This marks the acceptance of address and indicates the status of
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// write transaction.
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always @( posedge S_AXI_ACLK ) begin
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if ( S_AXI_ARESETN == 1'b0 ) begin
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axi_bvalid <= 0;
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axi_bresp <= 2'b0;
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end
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else begin
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if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID) begin
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// indicates a valid write response is available
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axi_bvalid <= 1'b1;
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axi_bresp <= 2'b0; // 'OKAY' response
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end // work error responses in future
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else begin
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if (S_AXI_BREADY && axi_bvalid) begin
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axi_bvalid <= 1'b0;
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end
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end
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end
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end
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// Implement axi_arready generation
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// axi_arready is asserted for one S_AXI_ACLK clock cycle when
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// S_AXI_ARVALID is asserted. axi_awready is
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// de-asserted when reset (active low) is asserted.
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// The read address is also latched when S_AXI_ARVALID is
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// asserted. axi_araddr is reset to zero on reset assertion.
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always @( posedge S_AXI_ACLK ) begin
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if ( S_AXI_ARESETN == 1'b0 ) begin
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axi_arready <= 1'b0;
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axi_araddr <= 32'b0;
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end
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else begin
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if (~axi_arready && S_AXI_ARVALID) begin
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// indicates that the slave has acceped the valid read address
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axi_arready <= 1'b1;
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// Read address latching
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axi_araddr <= S_AXI_ARADDR;
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end
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else begin
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axi_arready <= 1'b0;
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end
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end
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end
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// Implement axi_arvalid generation
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// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
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// S_AXI_ARVALID and axi_arready are asserted. The slave registers
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// data are available on the axi_rdata bus at this instance. The
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// assertion of axi_rvalid marks the validity of read data on the
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// bus and axi_rresp indicates the status of read transaction.axi_rvalid
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// is deasserted on reset (active low). axi_rresp and axi_rdata are
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// cleared to zero on reset (active low).
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always @( posedge S_AXI_ACLK ) begin
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if ( S_AXI_ARESETN == 1'b0 ) begin
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axi_rvalid <= 0;
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axi_rresp <= 0;
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end
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else begin
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if (axi_arready && S_AXI_ARVALID && ~axi_rvalid) begin
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// Valid read data is available at the read data bus
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axi_rvalid <= 1'b1;
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axi_rresp <= 2'b0; // 'OKAY' response
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end
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else if (axi_rvalid && S_AXI_RREADY) begin
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// Read data is accepted by the master
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axi_rvalid <= 1'b0;
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end
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end
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end
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// Output register or memory read data
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always @( posedge S_AXI_ACLK ) begin
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if ( S_AXI_ARESETN == 1'b0 ) begin
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axi_rdata <= 0;
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end
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else begin
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if (slv_reg_rden) begin
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axi_rdata <= reg_data_out; // register read data
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end
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end
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end
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// Implement memory mapped register select and write logic generation
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// The write data is accepted and written to memory mapped registers when
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// axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
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// select byte enables of slave registers while writing.
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// These registers are cleared when reset (active low) is applied.
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// Slave register write enable is asserted when valid address and data are available
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// and the slave is ready to accept the write address and write data.
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assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
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always @( posedge S_AXI_ACLK ) begin
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if ( S_AXI_ARESETN == 1'b0 ) begin
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slv_reg0 <= 0;
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slv_reg1 <= 0;
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slv_reg2 <= 0;
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slv_reg3 <= 0;
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end
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else begin
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if (slv_reg_wren) begin
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case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
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4'd0:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
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if ( S_AXI_WSTRB[byte_index] == 1 ) begin
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slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
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end
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4'd1:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
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if ( S_AXI_WSTRB[byte_index] == 1 ) begin
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slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
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end
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4'd2:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
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if ( S_AXI_WSTRB[byte_index] == 1 ) begin
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slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
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end
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4'd3:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
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if ( S_AXI_WSTRB[byte_index] == 1 ) begin
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slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
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end
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default :
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begin
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slv_reg0 <= slv_reg0;
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slv_reg1 <= slv_reg1;
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slv_reg2 <= slv_reg2;
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slv_reg3 <= slv_reg3;
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end
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endcase
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end
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end
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end
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// Implement memory mapped register select and read logic generation
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// Slave register read enable is asserted when valid address is available
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// and the slave is ready to accept the read address.
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assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
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always @(*) begin
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case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
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4'd0 : reg_data_out <= slv_reg0;
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4'd1 : reg_data_out <= slv_reg1;
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4'd2 : reg_data_out <= slv_reg2;
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4'd3 : reg_data_out <= slv_reg3;
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default : reg_data_out <= 0;
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endcase
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end
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// Add user logic here
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// User logic ends
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endmodule
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