924 lines
24 KiB
JSON
924 lines
24 KiB
JSON
{
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"IDDR": {
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"prefix": "iddr",
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"body" : [
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"IDDR #(",
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" // \"OPPOSITE_EDGE\", \"SAME_EDGE\" or \"SAME_EDGE_PIPELINED\" ",
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" .DDR_CLK_EDGE(\"SAME_EDGE\"), ",
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" .INIT_Q1(1'b0), // Initial value of Q1: 1'b0 or 1'b1",
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" .INIT_Q2(1'b0), // Initial value of Q2: 1'b0 or 1'b1",
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" .SRTYPE(\"SYNC\")) // Set/Reset type: \"SYNC\" or \"ASYNC\" ",
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"IDDR_inst (",
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"IDDR #(",
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" .Q1(rx_data_pos), // 1-bit output for positive edge of clock ",
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" .Q2(rx_data_neg), // 1-bit output for negative edge of clock",
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" .C(data_clk), // 1-bit clock input",
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" .CE(1'b1), // 1-bit clock enable input",
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" .D(rx_data_dly), // 1-bit DDR data input",
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" .R(1'b0), // 1-bit reset",
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" .S(1'b0) // 1-bit set",
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");"
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]
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},
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"ODDR": {
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"prefix": "oddr",
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"body" : [
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"ODDR #(",
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" .DDR_CLK_EDGE(\"SAME_EDGE\"), // \"OPPOSITE_EDGE\" or \"SAME_EDGE\" ",
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" .INIT(1'b0), // Initial value of Q: 1'b0 or 1'b1",
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" .SRTYPE(\"SYNC\")) // Set/Reset type: \"SYNC\" or \"ASYNC\" ",
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"ODDR_inst (",
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" .Q(odata), // 1-bit DDR output",
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" .C(data_clk), // 1-bit clock input",
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" .CE(1'b1), // 1-bit clock enable input",
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" .D1(data_p), // 1-bit data input (positive edge)",
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" .D2(data_n), // 1-bit data input (negative edge)",
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" .R(1'b0), // 1-bit reset",
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" .S(1'b0) // 1-bit set",
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");"
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]
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},
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"OBUFDS": {
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"prefix": "obuf",
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"body" : [
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"OBUFDS #(",
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" .IOSTANDARD(\"LVDS18\"), // Specify the output I/O standard",
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" .SLEW(\"SLOW\")) // Specify the output slew rate",
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"OBUFDS_inst (",
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" .O(tx_frame_p), // Diff_p output (connect directly to top-level port)",
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" .OB(tx_frame_n), // Diff_n output (connect directly to top-level port)",
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" .I(tx_frame) // Buffer input ",
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");"
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]
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},
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"IBUFDS": {
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"prefix": "ibuf",
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"body" : [
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"IBUFDS #(",
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" .DIFF_TERM(\"FALSE\"), // Differential Termination",
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" .IBUF_LOW_PWR(\"TRUE\"), // Low power=\"TRUE\", Highest performance=\"FALSE\" ",
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" .IOSTANDARD(\"DEFAULT\")) // Specify the input I/O standard",
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"IBUFDS_inst (",
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" .O(data_clk_tmp), // Buffer output",
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" .I(data_clk_p), // Diff_p buffer input (connect directly to top-level port)",
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" .IB(data_clk_n) // Diff_n buffer input (connect directly to top-level port)",
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");"
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]
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},
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"OSERDESE2": {
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"prefix": "oserd",
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"body" : [
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"OSERDESE2 #(",
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" .DATA_RATE_OQ(\"DDR\"), // DDR, SDR",
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" .DATA_RATE_TQ(\"DDR\"), // DDR, BUF, SDR",
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" .DATA_WIDTH(4), // Parallel data width (2-8,10,14)",
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" .INIT_OQ(1'b0), // Initial value of OQ output (1'b0,1'b1)",
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" .INIT_TQ(1'b0), // Initial value of TQ output (1'b0,1'b1)",
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" .SERDES_MODE(\"MASTER\"), // MASTER, SLAVE",
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" .SRVAL_OQ(1'b0), // OQ output value when SR is used (1'b0,1'b1)",
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" .SRVAL_TQ(1'b0), // TQ output value when SR is used (1'b0,1'b1)",
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" .TBYTE_CTL(\"FALSE\"), // Enable tristate byte operation (FALSE, TRUE)",
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" .TBYTE_SRC(\"FALSE\"), // Tristate byte source (FALSE, TRUE)",
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" .TRISTATE_WIDTH(4) // 3-state converter width (1,4)",
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")",
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"OSERDESE2_inst (",
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" .OFB(OFB), // 1-bit output: Feedback path for data",
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" .OQ(OQ), // 1-bit output: Data path output",
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" // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)",
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" .SHIFTOUT1(SHIFTOUT1),",
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" .SHIFTOUT2(SHIFTOUT2),",
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" .TBYTEOUT(TBYTEOUT), // 1-bit output: Byte group tristate",
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" .TFB(TFB), // 1-bit output: 3-state control",
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" .TQ(TQ), // 1-bit output: 3-state control",
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" .CLK(CLK), // 1-bit input: High speed clock",
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" .CLKDIV(CLKDIV), // 1-bit input: Divided clock",
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" // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)",
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" .D1(D1),",
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" .D2(D2),",
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" .D3(D3),",
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" .D4(D4),",
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" .D5(D5),",
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" .D6(D6),",
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" .D7(D7),",
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" .D8(D8),",
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" .OCE(OCE), // 1-bit input: Output data clock enable",
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" .RST(RST), // 1-bit input: Reset",
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" // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)",
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" .SHIFTIN1(SHIFTIN1),",
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" .SHIFTIN2(SHIFTIN2),",
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" // T1 - T4: 1-bit (each) input: Parallel 3-state inputs",
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" .T1(T1),",
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" .T2(T2),",
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" .T3(T3),",
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" .T4(T4),",
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" .TBYTEIN(TBYTEIN), // 1-bit input: Byte group tristate",
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" .TCE(TCE) // 1-bit input: 3-state clock enable",
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");"
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]
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},
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"ISERDESE2": {
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"prefix": "iserd",
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"body" : [
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"ISERDESE2 #(",
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" .DATA_RATE(\"DDR\"), // DDR, SDR",
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" .DATA_WIDTH(4), // Parallel data width (2-8,10,14)",
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" .DYN_CLKDIV_INV_EN(\"FALSE\"), // Enable DYNCLKDIVINVSEL inversion (FALSE, TRUE)",
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" .DYN_CLK_INV_EN(\"FALSE\"), // Enable DYNCLKINVSEL inversion (FALSE, TRUE)",
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" // INIT_Q1 - INIT_Q4: Initial value on the Q outputs (0/1)",
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" .INIT_Q1(1'b0),",
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" .INIT_Q2(1'b0),",
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" .INIT_Q3(1'b0),",
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" .INIT_Q4(1'b0),",
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" .INTERFACE_TYPE(\"MEMORY\"), // MEMORY, MEMORY_DDR3, MEMORY_QDR, NETWORKING, OVERSAMPLE",
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" .IOBDELAY(\"NONE\"), // NONE, BOTH, IBUF, IFD",
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" .NUM_CE(2), // Number of clock enables (1,2)",
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" .OFB_USED(\"FALSE\"), // Select OFB path (FALSE, TRUE)",
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" .SERDES_MODE(\"MASTER\"), // MASTER, SLAVE",
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" // SRVAL_Q1 - SRVAL_Q4: Q output values when SR is used (0/1)",
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" .SRVAL_Q1(1'b0),",
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" .SRVAL_Q2(1'b0),",
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" .SRVAL_Q3(1'b0),",
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" .SRVAL_Q4(1'b0))",
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"ISERDESE2_inst (",
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" .O(O), // 1-bit output: Combinatorial output",
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" // Q1 - Q8: 1-bit (each) output: Registered data outputs",
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" .Q1(Q1),",
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" .Q2(Q2),",
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" .Q3(Q3),",
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" .Q4(Q4),",
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" .Q5(Q5),",
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" .Q6(Q6),",
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" .Q7(Q7),",
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" .Q8(Q8),",
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" // SHIFTOUT1, SHIFTOUT2: 1-bit (each) output: Data width expansion output ports",
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" .SHIFTOUT1(SHIFTOUT1),",
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" .SHIFTOUT2(SHIFTOUT2),",
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"\n",
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" // 1-bit input: The BITSLIP pin performs a Bitslip operation synchronous to",
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" // CLKDIV when asserted (active High). Subsequently, the data seen on the Q1",
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" // to Q8 output ports will shift, as in a barrel-shifter operation, one",
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" // position every time Bitslip is invoked (DDR operation is different from",
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" // SDR).",
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" .BITSLIP(BITSLIP), ",
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"\n",
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" // CE1, CE2: 1-bit (each) input: Data register clock enable inputs",
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" .CE1(CE1),",
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" .CE2(CE2),",
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" .CLKDIVP(CLKDIVP), // 1-bit input: TBD",
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" // Clocks: 1-bit (each) input: ISERDESE2 clock input ports",
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" .CLK(CLK), // 1-bit input: High-speed clock",
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" .CLKB(CLKB), // 1-bit input: High-speed secondary clock",
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" .CLKDIV(CLKDIV), // 1-bit input: Divided clock",
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" .OCLK(OCLK), // 1-bit input: High speed output clock used when INTERFACE_TYPE=\"MEMORY\" ",
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" // Dynamic Clock Inversions: 1-bit (each) input: Dynamic clock inversion pins to switch clock polarity",
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" .DYNCLKDIVSEL(DYNCLKDIVSEL), // 1-bit input: Dynamic CLKDIV inversion",
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" .DYNCLKSEL(DYNCLKSEL), // 1-bit input: Dynamic CLK/CLKB inversion",
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" // Input Data: 1-bit (each) input: ISERDESE2 data input ports",
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" .D(D), // 1-bit input: Data input",
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" .DDLY(DDLY), // 1-bit input: Serial data from IDELAYE2",
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" .OFB(OFB), // 1-bit input: Data feedback from OSERDESE2",
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" .OCLKB(OCLKB), // 1-bit input: High speed negative edge output clock",
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" .RST(RST), // 1-bit input: Active high asynchronous reset",
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" // SHIFTIN1, SHIFTIN2: 1-bit (each) input: Data width expansion input ports",
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" .SHIFTIN1(SHIFTIN1),",
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" .SHIFTIN2(SHIFTIN2)",
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");"
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]
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},
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"count": {
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"prefix": "count",
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"body": [
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"//define the time counter",
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"reg [${1:32}:0] cnt$2 = 0;",
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"reg ${3:impulse};",
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"parameter SET_TIME = $1'd$4;",
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"always@(posedge clk) begin",
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" if (cnt$2 == SET_TIME) begin",
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" cnt$2 <= $1'd0;",
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" $3 <= 1'd1;",
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" end",
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" else begin",
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" cnt$2 <= cnt$2 + 1'd1;",
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" $3 <= 1'd0;",
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" end",
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"end"
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]
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},
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"divclk": {
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"prefix": "div",
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"body": [
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"reg [${1:3}:0] cnt$2 = 0;",
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"reg clk_div$2;",
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"always@(posedge ${3:clk}) begin",
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" if (cnt$2 == ${4:3}) begin",
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" cnt$2 <= $1'd0;",
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" clk_div$2 <= ~clk_div$2;",
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" end",
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" else begin",
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" cnt$2 <= cnt$2 + 1'd1;",
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" end",
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"end"
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]
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},
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"lock": {
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"prefix": "lock",
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"body": [
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"reg gate$2;",
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"reg gate$2_buf;",
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"wire gate$2_pose = gate$2 & ~gate$2_buf;",
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"wire gate$2_nege = ~gate$2 & gate$2_buf;",
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"always@(posedge clk) begin",
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" gate$2 <= ${1:signal};",
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" gate$2_buf <= gate$2;",
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"end"
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]
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},
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"posedge": {
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"prefix": "pos",
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"body": [
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"posedge"
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]
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},
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"negedge": {
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"prefix": "neg",
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"body": [
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"negedge"
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]
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},
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"resetn": {
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"prefix": "resetn",
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"body": [
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"reg rst_n_s1, rst_n_s2;",
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"wire rst_n",
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"always @ (posedge clk or negedge sys_rst_n) begin",
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" if (sys_rst_n) begin",
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" rst_n_s2 <= 1'b0;",
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" rst_n_s1 <= 1'b0;",
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" end",
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" rst_n_s1 <= 1'b1;",
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" rst_n_s2 <= rst_n_s1;",
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" end",
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"end",
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"assign rst_n = rst_n_s2;"
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],
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"description" : "Asynchronous sys_rst_n synchronous release (intel device)"
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},
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"reset": {
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"prefix": "reset",
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"body": [
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"reg rst_s1, rst_s2;",
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"wire rst",
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"always @ (posedge clk or posedge sys_rst) begin",
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" if (sys_rst) begin",
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" rst_s2 <= 1'b0;",
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" rst_s1 <= 1'b0;",
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" end",
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" rst_s1 <= 1'b1;",
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" rst_s2 <= rst_s1;",
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" end",
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"end",
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"assign rst = rst_s2;"
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],
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"description" : "Asynchronous sys_rst synchronous release (xilinx device)"
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},
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"initial sim": {
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"prefix": "inits",
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"body": [
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"initial begin",
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" \\$dumpfile(\"wave.vcd\");",
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" \\$dumpvars(0, ${1:testbench});",
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" #6000 \\$finish;",
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"end"
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],
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"description": "initial for simulation"
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},
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"initial array": {
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"prefix": "inita",
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"body": [
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"integer ${1:i};",
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"initial begin",
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" for ($1 = 0; $1<${2:range}; $1=$1+1) begin",
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" ${3:data}[$1] = 0;",
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" end",
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"end"
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],
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"description": "initial for a array"
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},
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"debug": {
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"prefix": "debug",
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"body": ["(* mark_debug = \"true\" *)"]
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},
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"time": {
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"prefix": "time",
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"body": ["`timescale 1ns / 1ps"]
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},
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"assign": {
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"prefix": "assign",
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"body": ["assign $1 = $2;"]
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},
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"always_ff block": {
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"prefix": "ff",
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"body": [
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"always_ff @( ${1:clock} ) begin : ${2:blockName}",
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" $0;",
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"end"
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],
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"description": "Insert an always_ff block"
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},
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"always_comb block": {
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"prefix": "comb",
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"body": [
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"always_comb begin : ${1:blockName}",
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" $0;",
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"end"
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],
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"description": "Insert an always_comb block"
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},
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"always": {
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"prefix": "alw",
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"body": [
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"always @(*) begin",
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" $1;",
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"end"
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],
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"description": "always @(*)"
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},
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"alwaysposclk": {
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"prefix": "alclk",
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"body": [
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"always @(posedge clk) begin",
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" $1;",
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"end"
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],
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"description": "always @(posedge clk) directly"
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},
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"alwayssyncrst": {
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"prefix": "alsync",
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"body": [
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"always @(posedge clk) begin",
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" if(rst) begin",
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" $1 <= 0;",
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" end",
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" else begin",
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" $2 <= $3;",
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" end",
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"end"
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],
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"description": "synchronous rst (xilinx device)"
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},
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"alwaysasyncrst": {
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"prefix": "alasync",
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"body": [
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"always @(posedge clk or posedge rst) begin",
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" if(rst) begin",
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" $1 <= 0;",
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" end",
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" else begin",
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" $2 <= $3;",
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" end",
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"end"
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],
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"description": "asynchronous rst (xilinx device)"
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},
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"alwayssyncrstn": {
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"prefix": "alsyncn",
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"body": [
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"always @(posedge clk) begin",
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" if(!rst_n) begin",
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" $1 <= 0;",
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" end",
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" else begin",
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" $2 <= $3;",
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" end",
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"end"
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],
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"description": "synchronous rst_n (intel device)"
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},
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"alwaysasyncrstn": {
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"prefix": "alasyncn",
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"body": [
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"always @(posedge clk or negedge rst_n) begin",
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" if(!rst_n) begin",
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" $1 <= 0;",
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" end",
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" else begin",
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" $2 <= $3;",
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" end",
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"end"
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],
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"description": "asynchronous rst_n (intel device)"
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},
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"beginend": {
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"prefix": "beginend",
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"body": [
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"begin",
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" $1",
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"end"
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],
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"description": "begin ... end"
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},
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"case": {
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"prefix": "case",
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"body": [
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"case (${1:conditions})",
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" $2: $3",
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"\tdefault: $4",
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"endcase"
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],
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"description": "case () ... endcase"
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},
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"module with parameters": {
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"prefix": "modp",
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"body": [
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"module ${1:name} #(",
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" parameter INPUT_WIDTH = ${2:12},",
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" parameter OUTPUT_WIDTH = $2",
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") (",
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" input clk,",
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" input RST,",
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" input [INPUT_WIDTH - 1 : 0] ${3:data_i},",
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" output [OUTPUT_WIDTH - 1 : 0] ${4:data_o}",
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");",
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" $5",
|
|
"endmodule //$1\n"
|
|
],
|
|
"description": "Insert a module with parameter"
|
|
},
|
|
|
|
"module without parameters": {
|
|
"prefix": "mod",
|
|
"body": [
|
|
"module ${1:moduleName} (",
|
|
" input clk,",
|
|
" input rst,",
|
|
" $2",
|
|
");",
|
|
" $3",
|
|
"endmodule //$1\n"
|
|
],
|
|
"description": "Insert a module without parameter"
|
|
},
|
|
"simple module": {
|
|
"prefix": "module",
|
|
"body": [
|
|
"module ${1:moduleName}($2);",
|
|
" $3",
|
|
"endmodule //$1\n"
|
|
],
|
|
"description": "Insert a common module"
|
|
},
|
|
"generate_for": {
|
|
"prefix": "genfor",
|
|
"body": [
|
|
"genvar ${1:i};",
|
|
"generate for($1 = 0 ; $1 < $2; $1 = $1 + 1) begin : ${3:U}",
|
|
" $4",
|
|
"end",
|
|
"endgenerate"
|
|
]
|
|
},
|
|
|
|
"generate_if": {
|
|
"prefix": "genif",
|
|
"body": [
|
|
"generate if(${1:conditional}) begin : ${2:U}",
|
|
" ${3:}",
|
|
"end",
|
|
"endgenerate"
|
|
]
|
|
},
|
|
|
|
"generate_case": {
|
|
"prefix": "gencase",
|
|
"body": [
|
|
"generate",
|
|
"case (${1:NUM})",
|
|
"32'd1 : begin : ${2:case1_name}",
|
|
"$3",
|
|
" end",
|
|
"32'd2 : begin : ${4:case1_name}",
|
|
"$5",
|
|
" end",
|
|
"default : begin : NOP end",
|
|
"endcase",
|
|
"endgenerate"
|
|
]
|
|
},
|
|
|
|
"if block": {
|
|
"prefix": "if",
|
|
"body": [
|
|
"if (${1:conditions}) begin",
|
|
" $0",
|
|
"end"
|
|
],
|
|
"description": "Insert a if block"
|
|
},
|
|
|
|
"include": {
|
|
"prefix": "include",
|
|
"body": [
|
|
"`include \"$1\""
|
|
],
|
|
"description": "`include \"..\""
|
|
},
|
|
|
|
"define": {
|
|
"prefix": "define",
|
|
"body": [
|
|
"`define $1 $2"
|
|
],
|
|
"description": "`define var = val"
|
|
},
|
|
|
|
"parameter": {
|
|
"prefix": "param",
|
|
"body": [
|
|
"parameter $1 = $2;"
|
|
],
|
|
"description": "paramter var = val;"
|
|
},
|
|
|
|
"localparam": {
|
|
"prefix": "param",
|
|
"body": [
|
|
"localparam $1 = $2;"
|
|
],
|
|
"description": "localparam var = val;"
|
|
},
|
|
|
|
"ifelse": {
|
|
"prefix": "ifelse",
|
|
"body": [
|
|
"if (${1:conditions}) begin",
|
|
" $2",
|
|
"end",
|
|
"else begin",
|
|
" $3",
|
|
"end"
|
|
],
|
|
"description": "if (...) begin ... end else begin ... end"
|
|
},
|
|
|
|
"else": {
|
|
"prefix": "else",
|
|
"body": [
|
|
"else begin",
|
|
" $1",
|
|
"end"
|
|
],
|
|
"description": "else begin ... end"
|
|
},
|
|
|
|
"elseif": {
|
|
"prefix": "elif",
|
|
"body": [
|
|
"else if(${1:conditions}) begin",
|
|
" $2",
|
|
"end"
|
|
],
|
|
"description": "else if(conditions) begin ... end"
|
|
},
|
|
|
|
"for loop": {
|
|
"prefix": "for",
|
|
"body": [
|
|
"for ($1 = $2; $3; $4) begin",
|
|
" $0",
|
|
"end"
|
|
],
|
|
"description": "for (...) begin ... end"
|
|
},
|
|
|
|
"while loop": {
|
|
"prefix": "while",
|
|
"body": [
|
|
"while ($1) begin",
|
|
" $2",
|
|
"end"
|
|
],
|
|
"description": "while (...) begin ... end"
|
|
},
|
|
|
|
"function": {
|
|
"prefix": "function",
|
|
"body": [
|
|
"function $1;",
|
|
" $2;",
|
|
" $3",
|
|
"endfunction"
|
|
],
|
|
"description": "function (...) ... endfunction"
|
|
},
|
|
|
|
"bit":{
|
|
"prefix":"bit",
|
|
"body":"bit"
|
|
},
|
|
|
|
"int":{
|
|
"prefix":"int",
|
|
"body":"int"
|
|
},
|
|
|
|
"byte":{
|
|
"prefix":"byte",
|
|
"body":"byte"
|
|
},
|
|
|
|
"logic":{
|
|
"prefix":"logic",
|
|
"body":"logic"
|
|
},
|
|
|
|
"reg": {
|
|
"prefix": "reg",
|
|
"body": [
|
|
"reg $1;"
|
|
],
|
|
"description": "reg reg_name;"
|
|
},
|
|
|
|
"regarray": {
|
|
"prefix": "rega",
|
|
"body": [
|
|
"reg [$1:$2] $3;"
|
|
],
|
|
"description": "reg [N:0] reg_name;"
|
|
},
|
|
|
|
"regmemory": {
|
|
"prefix": "regm",
|
|
"body": [
|
|
"reg [$1:$2] $3 [$4:$5];"
|
|
],
|
|
"description": "reg [N:0] reg_name [0:M];"
|
|
},
|
|
|
|
"wire": {
|
|
"prefix": "wire",
|
|
"body": [
|
|
"wire $1;"
|
|
],
|
|
"description": "wire wire_name;"
|
|
},
|
|
|
|
"wirearray": {
|
|
"prefix": "wirea",
|
|
"body": [
|
|
"wire [$1:$2] $3;"
|
|
],
|
|
"description": "wire [N:0] wire_name;"
|
|
},
|
|
|
|
"packed":{
|
|
"prefix":"packed",
|
|
"body":"packed"
|
|
},
|
|
|
|
"this":{
|
|
"prefix": "this",
|
|
"body": "this"
|
|
},
|
|
|
|
"array":{
|
|
"prefix":"array",
|
|
"body":"[${1:8}:${2:0}]$0",
|
|
"description":"insert [x:y]"
|
|
},
|
|
|
|
"typedef struct packed":{
|
|
"prefix":"typedefstructpacked",
|
|
"body":[
|
|
"typedef struct packed {",
|
|
" $0",
|
|
"} ${1:struct_name};"
|
|
],
|
|
"description":"typedef struct packed { ... } name"
|
|
},
|
|
|
|
"class":{
|
|
"prefix":"class",
|
|
"body":[
|
|
"class ${1:className};",
|
|
"\tfunction new();",
|
|
" $0",
|
|
"\tendfunction //new()",
|
|
"endclass //${1}"
|
|
],
|
|
"description":"class name; ... endclass"
|
|
},
|
|
|
|
"class extends":{
|
|
"prefix":"classextends",
|
|
"body":[
|
|
"class ${1:className} extends ${2:superClass};",
|
|
"\tfunction new();",
|
|
" $0",
|
|
"\tendfunction //new()",
|
|
"endclass //${1} extends ${2}"
|
|
],
|
|
"description":"class name extends super; ... endclass"
|
|
},
|
|
|
|
"task":{
|
|
"prefix":"task",
|
|
"body":[
|
|
"task ${1:automatic} ${2:taskName}(${3:arguments});",
|
|
" $0",
|
|
"endtask //${1}"
|
|
],
|
|
"description":"task name; ... endtask"
|
|
},
|
|
|
|
"interface":{
|
|
"prefix":"interface",
|
|
"body":[
|
|
"interface ${1:interfacename};",
|
|
" $0",
|
|
"endinterface //${1}"
|
|
],
|
|
"description":"interface name; ... endinterface"
|
|
},
|
|
|
|
"display":{
|
|
"prefix":"display",
|
|
"body":[
|
|
"\\$display($0);"
|
|
],
|
|
"description":"$display(\"...\", params...)"
|
|
},
|
|
|
|
"set Module":{
|
|
"prefix":"setmodule",
|
|
"body":[
|
|
"${1:mod_name} ${2:instance_name} (${3:.*}$0);"
|
|
],
|
|
"description":"set module, mod i0 (.*);"
|
|
},
|
|
|
|
"typedef enum":{
|
|
"prefix":"typedefenum",
|
|
"body":[
|
|
"typedef enum ${1:data_type} { $0 } ${2:name};"
|
|
],
|
|
"description":"typedef enum (data_type) { ... } name"
|
|
},
|
|
|
|
"enum":{
|
|
"prefix":"enum",
|
|
"body":[
|
|
"enum ${1:data_type} { $0 } ${2:name}"
|
|
],
|
|
"description":"enum (data_type) { ... } name"
|
|
},
|
|
|
|
"queue":{
|
|
"prefix":"queue",
|
|
"body":"${1:data_type} ${2:queue_name}[$];",
|
|
"description":"insert queue."
|
|
},
|
|
|
|
"mailbox":{
|
|
"prefix":"mailbox",
|
|
"body":[
|
|
"mailbox mbx",
|
|
"${1:mbx = new();}"
|
|
],
|
|
"description":"insert mailbox instance"
|
|
},
|
|
|
|
"Associative array":{
|
|
"prefix":"AA",
|
|
"body":"${1:data_type} ${2:name}[${3:index_type}];$0",
|
|
"description":"insert Associative array(AA)."
|
|
},
|
|
|
|
"assert":{
|
|
"prefix": "assert",
|
|
"body": [
|
|
"assert (${1:condition}) ${2}",
|
|
"else ${3:error_process}"
|
|
],
|
|
"description": "insert assert() ... else ..."
|
|
},
|
|
|
|
"fork-join":{
|
|
"prefix": "forkjoin",
|
|
"body": [
|
|
"fork",
|
|
" $0",
|
|
"join"
|
|
],
|
|
"description": "fork ... join"
|
|
},
|
|
|
|
"forever":{
|
|
"prefix": "forever",
|
|
"body": [
|
|
"forever begin",
|
|
" $0",
|
|
"end"
|
|
],
|
|
"description": "forever begin ... end"
|
|
},
|
|
|
|
"write":{
|
|
"prefix": "$write",
|
|
"body": [
|
|
"\\$write($1)"
|
|
],
|
|
"description": ""
|
|
},
|
|
|
|
"clog2":{
|
|
"prefix": "$clog2",
|
|
"body": [
|
|
"\\$clog2($1)"
|
|
],
|
|
"description": ""
|
|
},
|
|
|
|
"signed":{
|
|
"prefix": "$signed",
|
|
"body": [
|
|
"\\$signed($1)"
|
|
],
|
|
"description": ""
|
|
},
|
|
|
|
"unsigned":{
|
|
"prefix": "$unsigned",
|
|
"body": [
|
|
"\\$unsigned($1)"
|
|
],
|
|
"description": ""
|
|
},
|
|
|
|
"random" : {
|
|
"prefix": "$random",
|
|
"body": [
|
|
"\\$random($1)"
|
|
],
|
|
"description": ""
|
|
},
|
|
|
|
"wavedrom comment": {
|
|
"prefix" : "wavedrom",
|
|
"body": [
|
|
"/* @wavedrom",
|
|
"{",
|
|
" $1",
|
|
"}",
|
|
"*/"
|
|
]
|
|
},
|
|
"dumpfile": {
|
|
"prefix": "$dumpfile",
|
|
"body": [
|
|
"\\$dumpfile(\"$1\");"
|
|
]
|
|
},
|
|
"dumpvars": {
|
|
"prefix": "$dumpvars",
|
|
"body": [
|
|
"\\$dumpvars;"
|
|
]
|
|
},
|
|
"finish": {
|
|
"prefix": "$finish",
|
|
"body": [
|
|
"\\$finish;"
|
|
]
|
|
}
|
|
} |