digital-ide/syntaxes/systemverilog.json
2025-03-02 23:43:58 +08:00

471 lines
18 KiB
JSON

{
"fileTypes": [
"sv",
"svh",
"v",
"vh"
],
"hidden": true,
"name": "SystemVerilog",
"patterns": [
{
"include": "#comments"
},
{
"include": "#module_pattern"
},
{
"include": "#keywords"
},
{
"include": "#constants"
},
{
"include": "#strings"
},
{
"include": "#operators"
},
{
"include": "#macro_definition"
},
{
"include": "#macro_quote"
},
{
"include": "#common_variable"
}
],
"repository": {
"comments": {
"patterns": [
{
"include": "#wavedrom_comment"
},
{
"begin": "(^[ \\t]+)?(?=//)",
"beginCaptures": {
"1": {
"name": "punctuation.whitespace.comment.leading.verilog"
}
},
"end": "(?!\\G)",
"patterns": [
{
"begin": "//",
"beginCaptures": {
"0": {
"name": "punctuation.definition.comment.verilog"
}
},
"end": "\\n",
"name": "comment.line.double-slash.verilog"
}
]
},
{
"begin": "/\\*",
"end": "\\*/",
"name": "comment.block.c-style.verilog"
}
]
},
"constants": {
"patterns": [
{
"match": "\\b[0-9]+'[bBoOdDhH][a-fA-F0-9_xXzZ]+\\b",
"name": "constant.numeric.sized_integer.verilog"
},
{
"captures": {
"1": {
"name": "constant.numeric.integer.verilog"
},
"2": {
"name": "punctuation.separator.range.verilog"
},
"3": {
"name": "constant.numeric.integer.verilog"
}
},
"match": "\\b(\\d+)(:)(\\d+)\\b",
"name": "meta.block.numeric.range.verilog"
},
{
"match": "\\b\\d+(?i:e\\d+)?\\b",
"name": "constant.numeric.integer.verilog"
},
{
"match": "\\b\\d+\\.\\d+(?i:e\\d+)?\\b",
"name": "constant.numeric.real.verilog"
},
{
"match": "#\\d+",
"name": "constant.numeric.delay.verilog"
},
{
"match": "\\b[01xXzZ]+\\b",
"name": "constant.numeric.logic.verilog"
}
]
},
"instantiation_patterns": {
"patterns": [
{
"include": "#keywords"
},
{
"begin": "^\\s*([a-zA-Z][a-zA-Z0-9_]*)\\s+([a-zA-Z][a-zA-Z0-9_]*)(?<!begin|if)\\s*(?=\\(|$)",
"beginCaptures": {
"1": {
"name": "entity.name.class.module.reference.verilog"
},
"2": {
"name": "entity.name.function.module.identifier.verilog"
}
},
"end": ";",
"endCaptures": {
"0": {
"name": "punctuation.terminator.expression.verilog"
}
},
"name": "variable.other.constant.instantiation.parameterless.verilog",
"patterns": [
{
"include": "#comments"
},
{
"include": "#constants"
},
{
"include": "#strings"
}
]
},
{
"begin": "^\\s*([a-zA-Z][a-zA-Z0-9_]*)\\s*(#)(?=\\s*\\()",
"beginCaptures": {
"1": {
"name": "entity.name.class.module.reference.verilog"
}
},
"end": ";",
"endCaptures": {
"0": {
"name": "punctuation.terminator.expression.verilog"
}
},
"name": "support.block.instantiation.with.parameters.verilog",
"patterns": [
{
"include": "#parenthetical_list"
},
{
"match": "[a-zA-Z][a-zA-Z0-9_]*",
"name": "entity.name.function.module.identifier.verilog"
}
]
}
]
},
"keywords": {
"patterns": [
{
"match": "\\b(always|and|assign|attribute|begin|buf|bufif0|bufif1|case(xz)?|cmos|deassign|default|defparam|disable|edge|else|end(attribute|case|function|generate|module|primitive|specify|table|task)?|event|for|force|forever|fork|function|generate|genvar|highz(01)|if(none)?|initial|inout|input|output|integer|join|localparam|medium|module|large|macromodule|nand|negedge|nmos|nor|not|notif(01)|or|parameter|pmos|posedge|primitive|pull0|pull1|pulldown|pullup|rcmos|real|realtime|reg|release|repeat|rnmos|rpmos|rtran|rtranif(01)|scalared|signed|small|specify|specparam|strength|strong0|strong1|supply0|supply1|table|task|time|tran|tranif(01)|tri(01)?|tri(and|or|reg)|unsigned|vectored|wait|wand|weak(01)|while|wire|wor|xnor|xor|logic)\\b",
"name": "keyword.other.verilog"
},
{
"match": "\\b(initial|always|wait|force|release|assign|always_comb|always_ff|always_latch|forever|repeat|while|for|if|iff|else|case|casex|casez|default|endcase|return|break|continue|do|foreach|with|inside|dist|clocking|cover|coverpoint|property|bins|binsof|illegal_bins|ignore_bins|randcase|modport|matches|solve|static|assert|assume|before|expect|cross|ref|first_match|srandom|struct|packed|final|chandle|alias|tagged|extern|throughout|timeprecision|timeunit|priority|type|union|uwire|wait_order|triggered|randsequence|import|export|context|pure|intersect|wildcard|within|new|typedef|enum|this|super|begin|fork|forkjoin|unique|unique0|priority)\\b",
"name": "keyword.other.systemverilog"
},
{
"match": "\\s*\\b(end|endtask|endmodule|endfunction|endprimitive|endclass|endpackage|endsequence|endprogram|endclocking|endproperty|endgroup|endinterface|join|join_any|join_none)\\b(\\s*(:)\\s*(\\w+))?",
"captures": {
"1": {
"name": "keyword.control.systemverilog"
},
"3": {
"name": "keyword.operator.systemverilog"
},
"4": {
"name": "entity.label.systemverilog"
}
},
"name": "meta.object.end.systemverilog"
},
{
"match": "\\b(std)\\b::",
"name": "support.class.systemverilog"
},
{
"captures": {
"1": {
"name": "keyword.control.systemverilog"
},
"2": {
"name": "keyword.control.systemverilog"
},
"3": {
"name": "entity.name.type.class.systemverilog"
}
},
"match": "\\b(virtual\\s+)?(class)\\s+\\b([a-zA-Z_][a-zA-Z0-9_]*)\\b",
"name": "meta.definition.class.systemverilog"
},
{
"match": "^\\s*`((cell)?define|default_(decay_time|nettype|trireg_strength)|delay_mode_(path|unit|zero)|ifdef|include|end(if|celldefine)|else|(no)?unconnected_drive|resetall|timescale|undef)\\b",
"name": "keyword.other.compiler.directive.verilog"
},
{
"match": "\\$(f(open|close)|readmem(b|h)|timeformat|printtimescale|stop|finish|(s|real)?time|realtobits|bitstoreal|rtoi|itor|(f)?(display|write(h|b)))\\b",
"name": "support.function.system.console.tasks.verilog"
},
{
"match": "\\$(random|dist_(chi_square|erlang|exponential|normal|poisson|t|uniform))\\b",
"name": "support.function.system.random_number.tasks.verilog"
},
{
"match": "\\$((a)?sync\\$((n)?and|(n)or)\\$(array|plane))\\b",
"name": "support.function.system.pld_modeling.tasks.verilog"
},
{
"match": "\\$(q_(initialize|add|remove|full|exam))\\b",
"name": "support.function.system.stochastic.tasks.verilog"
},
{
"match": "\\$(hold|nochange|period|recovery|setup(hold)?|skew|width)\\b",
"name": "support.function.system.timing.tasks.verilog"
},
{
"match": "\\$(dump(file|vars|off|on|all|limit|flush))\\b",
"name": "support.function.system.vcd.tasks.verilog"
},
{
"match": "\\$(countdrivers|list|input|scope|showscopes|(no)?(key|log)|reset(_count|_value)?|(inc)?save|restart|showvars|getpattern|sreadmem(b|h)|scale)",
"name": "support.function.non-standard.tasks.verilog"
}
]
},
"module_pattern": {
"patterns": [
{
"begin": "\\b(module)\\s+([a-zA-Z][a-zA-Z0-9_]*)",
"beginCaptures": {
"1": {
"name": "storage.type.module.verilog"
},
"2": {
"name": "entity.name.type.module.verilog"
}
},
"end": "\\bendmodule\\b",
"endCaptures": {
"0": {
"name": "storage.type.module.verilog"
}
},
"name": "meta.block.module.verilog",
"patterns": [
{
"include": "#comments"
},
{
"include": "#keywords"
},
{
"include": "#constants"
},
{
"include": "#strings"
},
{
"include": "#operators"
},
{
"include": "#position_ports"
},
{
"include": "#macro_quote"
},
{
"include": "#common_variable"
}
]
}
]
},
"operators": {
"patterns": [
{
"match": "\\+|-|\\*|/|%|(<|>)=?|(!|=)?==?|!|&&?|\\|\\|?|\\^?~|~\\^?",
"name": "keyword.operator.verilog"
}
]
},
"parenthetical_list": {
"patterns": [
{
"begin": "\\(",
"beginCaptures": {
"0": {
"name": "punctuation.section.list.verilog"
}
},
"end": "\\)",
"endCaptures": {
"0": {
"name": "punctuation.section.list.verilog"
}
},
"name": "support.block.parenthetical_list.verilog",
"patterns": [
{
"include": "#parenthetical_list"
},
{
"include": "#comments"
},
{
"include": "#keywords"
},
{
"include": "#constants"
},
{
"include": "#strings"
},
{
"include": "#position_ports"
},
{
"include": "#macro_quote"
},
{
"include": "#common_variable"
}
]
}
]
},
"position_ports": {
"patterns": [
{
"match": "\\.[a-zA-Z_][a-zA-Z_0-9]*",
"name": "variable.inst.port.verilog"
}
]
},
"strings": {
"patterns": [
{
"begin": "\"",
"end": "\"",
"name": "string.quoted.double.verilog",
"patterns": [
{
"match": "\\\\.",
"name": "constant.character.escape.verilog"
}
]
}
]
},
"macro_definition": {
"patterns": [
{
"match": "(?<=`define\\s)\\w+",
"name": "support.function.macro.definition.verilog"
}
]
},
"macro_quote": {
"patterns": [
{
"match": "`[a-zA-Z_][a-zA-Z_0-9]*",
"name": "support.function.macro.quote.verilog"
}
]
},
"common_variable": {
"patterns": [
{
"match": "[a-zA-Z_][a-zA-Z_0-9]*",
"name": "variable.other.constant.verilog"
}
]
},
"wavedrom_comment": {
"begin": "\\s*(/\\*)\\s*(@wavedrom)\\s*([\\S\\s]*)",
"beginCaptures": {
"0": {
"name": "meta.psl.verilog"
},
"1": {
"name": "comment.block.verilog"
},
"2": {
"name": "keyword.comment.special.verilog"
},
"3": {
"name": "comment.block.verilog"
},
"4": {
"name": "comment.block.verilog"
}
},
"end": "(\\*/)",
"endCaptures": {
"1": {
"name": "comment.block.verilog"
}
},
"patterns": [
{
"match": "\\s*(signal|assign|reg)",
"captures": {
"0": {
"name": "keyword.wavedrom.verilog"
},
"2": {
"name": "entity.wavedrom.name.verilog"
},
"3": {
"name": "keyword.operator.verilog"
}
}
},
{
"match": "\\s*(name|wave|data)",
"captures": {
"0": {
"name": "variable.wavedrom.verilog"
},
"2": {
"name": "entity.wavedrom.name.verilog"
},
"3": {
"name": "keyword.operator.verilog"
},
"4": {
"name": "variable.wavedrom.verilog"
}
}
},
{
"include": "#operators"
},
{
"include": "#constants"
},
{
"include" : "#strings"
}
],
"name": "meta.comment.wavedrom"
}
},
"scopeName": "source.systemverilog",
"uuid": "789be04c-8b74-352e-8f37-63d336001277"
}