34 lines
804 B
Verilog
34 lines
804 B
Verilog
module AGC(
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input wire clk,
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input wire rst,
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input wire [7:0] a_coef,
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input wire [15:0] reference,
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input wire signed [15:0] x_in,
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output wire signed [15:0] y_out
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);
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wire [31:0] x_mod;
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wire [31:0] ref_rms;
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wire signed [8:0] a_coef_s;
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wire signed [32:0] tmp_level;
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wire signed [32:0] feedback_level;
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reg signed [32:0] zreg;
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assign ref_rms = (reference[15:1] * reference[15:1]);
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assign a_coef_s = { 1'b0, a_coef};
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assign x_mod = (y_out * y_out);
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assign tmp_level = ($signed(ref_rms - x_mod))>>>18;
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assign feedback_level = (tmp_level * a_coef_s) >>> 8;
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always @(posedge clk or negedge rst) begin
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if (!rst)
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zreg <= 'h0;
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else
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zreg <= zreg + feedback_level;
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end
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assign y_out = (zreg * x_in) >>>16;
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endmodule
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