18 lines
241 B
Verilog
18 lines
241 B
Verilog
`timescale 1ns / 1ps
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module manchester (
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input clk,
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input sig_in,
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output man_sig_out
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);
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reg ck = 0;
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reg ck_r = 0;
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always @(posedge clk) begin
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ck <= ck_r;
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ck <= ~ ck;
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end
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assign man_sig_out = ck ^ sig_in;
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endmodule
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