26 lines
451 B
Verilog
26 lines
451 B
Verilog
`timescale 1ns / 1ps
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module mseq #(
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parameter W = 4'd4,
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parameter POLY = 5'b10011
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) (
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input clk,
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input rst_n,
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output mseq_out
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);
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reg [W-1:0] sreg = 8'b11111111;
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assign mseq_out = sreg[0];
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always@(posedge clk or posedge rst_n) begin
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if(~rst_n)
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sreg <= 1'b1;
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else begin
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if(mseq_out)
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sreg <= (sreg >> 1) ^ (POLY >> 1);
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else
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sreg <= sreg >> 1;
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end
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end
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endmodule
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