149 lines
4.1 KiB
Verilog
149 lines
4.1 KiB
Verilog
//--------------------------------------------------------------------------------------------
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//
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// Generated by X-HDL VHDL Translator - Version 2.0.0 Feb. 1, 2011
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// ?? 3? 29 2020 15:44:24
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//
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// Input file :
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// Component name : multiplier
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// Author :
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// Company :
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//
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// Description :
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//
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//
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//--------------------------------------------------------------------------------------------
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module multiplier(CLK, RESET, input1, input2, output_xhdl0);
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input CLK;
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input RESET;
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input [7:0] input1;
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input [7:0] input2;
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output [7:0] output_xhdl0;
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reg [7:0] output_xhdl0;
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reg [15:0] out_temp;
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reg [15:0] input1_buf;
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reg [15:0] part0;
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reg [15:0] part1;
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reg [15:0] part2;
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reg [15:0] part3;
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reg [15:0] part4;
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reg [15:0] part5;
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reg [15:0] part6;
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reg [15:0] part7;
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always @(posedge CLK or posedge RESET)
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if (RESET == 1'b1)
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begin
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out_temp <= {16{1'b0}};
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output_xhdl0 <= {8{1'b0}};
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input1_buf <= {16{1'b0}};
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part0 <= {16{1'b0}};
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part1 <= {16{1'b0}};
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part2 <= {16{1'b0}};
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part3 <= {16{1'b0}};
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part4 <= {16{1'b0}};
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part5 <= {16{1'b0}};
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part6 <= {16{1'b0}};
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part7 <= {16{1'b0}};
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end
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else
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begin
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input1_buf <= {input1[7], input1[7], input1[7], input1[7], input1[7], input1[7], input1[7], input1[7], signed_xhdl1(input1)};
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if (input2[0] == 1'b1)
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part0 <= -(input1_buf);
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else
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part0 <= {16{1'b0}};
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if (input2[1] == 1'b1)
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begin
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if (input2[0] == 1'b1)
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part1 <= {16{1'b0}};
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else
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part1 <= -(input1_buf);
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end
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else
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if (input2[0] == 1'b1)
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part1 <= input1_buf;
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else
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part1 <= {16{1'b0}};
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if (input2[2] == 1'b1)
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begin
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if (input2[1] == 1'b1)
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part2 <= {16{1'b0}};
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else
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part2 <= -(input1_buf);
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end
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else
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if (input2[1] == 1'b1)
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part2 <= input1_buf;
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else
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part2 <= {16{1'b0}};
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if (input2[3] == 1'b1)
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begin
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if (input2[2] == 1'b1)
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part3 <= {16{1'b0}};
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else
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part3 <= -(input1_buf);
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end
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else
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if (input2[2] == 1'b1)
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part3 <= input1_buf;
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else
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part3 <= {16{1'b0}};
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if (input2[4] == 1'b1)
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begin
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if (input2[3] == 1'b1)
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part4 <= {16{1'b0}};
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else
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part4 <= -(input1_buf);
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end
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else
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if (input2[3] == 1'b1)
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part4 <= input1_buf;
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else
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part4 <= {16{1'b0}};
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if (input2[5] == 1'b1)
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begin
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if (input2[4] == 1'b1)
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part5 <= {16{1'b0}};
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else
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part5 <= -(input1_buf);
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end
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else
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if (input2[4] == 1'b1)
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part5 <= input1_buf;
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else
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part5 <= {16{1'b0}};
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if (input2[6] == 1'b1)
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begin
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if (input2[5] == 1'b1)
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part6 <= {16{1'b0}};
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else
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part6 <= -(input1_buf);
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end
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else
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if (input2[5] == 1'b1)
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part6 <= input1_buf;
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else
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part6 <= {16{1'b0}};
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if (input2[7] == 1'b1)
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begin
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if (input2[6] == 1'b1)
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part7 <= {16{1'b0}};
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else
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part7 <= -(input1_buf);
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end
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else
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if (input2[6] == 1'b1)
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part7 <= input1_buf;
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else
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part7 <= {16{1'b0}};
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out_temp <= part0 + ({part1[14:0], 1'b0}) + ({part2[13:0], 2'b00}) + ({part3[12:0], 3'b000}) + ({part4[11:0], 4'b0000}) + ({part5[10:0], 5'b00000}) + ({part6[9:0], 6'b000000}) + ({part7[8:0], 7'b0000000});
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output_xhdl0 <= out_temp[15:8];
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end
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endmodule
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