101 lines
2.0 KiB
Verilog
101 lines
2.0 KiB
Verilog
module Max_meas #
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(
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parameter data_width = 4'd12,
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parameter range_width = 4'd10
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)
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(
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input clk_in,
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input rst_n,
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input [range_width-1:0] range,
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input signed [data_width - 1:0] data_in,
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output signed [data_width - 1:0] data_out
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);
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localparam state_output = 3'b010;
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localparam state_initial = 3'b000;
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localparam state_detection = 3'b001;
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reg signed [data_width - 1:0] data_out_buf = 0;
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reg signed [data_width - 1:0] data_out_buf1 = 0;
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reg [2:0] state = 3'b000;
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reg test_sig = 1'b0;
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reg test_sig_buf = 1'b0;
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wire test_done_sig = ~test_sig & test_sig_buf;
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wire test_start_sig = test_sig & ~test_sig_buf;
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/***************************************************/
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//define the time counter
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reg [range_width-1:0] cnt0 = 1;
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always@(posedge clk_in)
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begin
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if (range == 0)
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begin
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test_sig <= 1'b1;
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end
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else if (cnt0 == range)
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begin
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cnt0 <= 10'd0; //count done,clearing the time counter
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test_sig <= 1'd0;
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end
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else
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test_sig <= 1'd1; //cnt0 counter = cnt0 counter + 1
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cnt0 <= cnt0 + 1'b1;
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end
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/***************************************************/
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always@(posedge clk_in)
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begin
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if (range == 0)
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begin
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test_sig_buf <= 1'b0;
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end
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else
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begin
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test_sig_buf <= test_sig;
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end
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end
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always@(posedge clk_in or negedge rst_n)
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begin
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if(!rst_n)
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begin
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data_out_buf <= 0;
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data_out_buf1 <= 0;
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end
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else
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begin
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case(state)
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state_initial:begin
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if(test_start_sig)
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begin
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state <= state_detection;
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data_out_buf <= 0;
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end
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end
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state_detection:begin
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if(test_done_sig)
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state <= state_output;
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else
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if(data_in > data_out_buf)
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begin
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data_out_buf <= data_in;
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if (range == 0)
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begin
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data_out_buf1 <= data_out_buf;
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end
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end
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end
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state_output:begin
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data_out_buf1 <= data_out_buf;
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state <= state_initial;
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end
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endcase
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end
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end
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assign data_out=data_out_buf1;
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endmodule
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