17 lines
296 B
Verilog
17 lines
296 B
Verilog
module AD6645
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(
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input clk_in,
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input rst_n,
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input [13:0] AD_data,
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output [13:0] wave_CH
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);
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reg [13:0] wave_CH_buf;
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always@(posedge clk_in or negedge rst_n)
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begin
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if(!rst_n)
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wave_CH_buf <= 14'd0;
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else
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wave_CH_buf <= AD_data;
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end
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assign wave_CH = wave_CH_buf - 14'd1700;
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endmodule
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