251 lines
7.3 KiB
VHDL
251 lines
7.3 KiB
VHDL
----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 2016/04/06 13:55:20
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-- Design Name:
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-- Module Name: CFG_INT - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_unsigned.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity CFG_INT is
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Port (
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CLK : in STD_LOGIC;--100mhz
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RSTn : in STD_LOGIC;
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TRIG : in STD_LOGIC;
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ADDR : in STD_LOGIC_VECTOR(7 downto 0);
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DATA : in STD_LOGIC_VECTOR(7 downto 0);
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SCLK : out STD_LOGIC;
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SDATA : out STD_LOGIC;
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SEN : out STD_LOGIC;
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BUSY : out STD_LOGIC
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);
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end CFG_INT;
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architecture Behavioral of CFG_INT is
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type state_type is (idle,start,wr_addr,wr_data,done);
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signal state : state_type;
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signal freq_div : std_logic_vector(3 downto 0);
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signal trig_r : std_logic;
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signal trig_rr : std_logic;
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signal trigger : std_logic;
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signal addr_i : std_logic_vector(7 downto 0);
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signal addr_r : std_logic_vector(7 downto 0);
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signal data_i : std_logic_vector(7 downto 0);
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signal data_r : std_logic_vector(7 downto 0);
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signal sen_i : std_logic;
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signal bit_count : std_logic_vector(3 downto 0);
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signal sclk_r : std_logic;
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signal sclk_f : std_logic;
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signal sclk_flag : std_logic;
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signal sclk_i : std_logic;
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signal sdata_i : std_logic;
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signal busy_i : std_logic;
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begin
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process(clk,rstn)
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begin
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if rstn='0' then
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trig_r<='0';
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trig_rr<='0';
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elsif rising_edge(clk) then
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trig_r<=trig;
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trig_rr<=trig_r;
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end if;
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end process;
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trigger<='1' when trig_r='1' and trig_rr='0' else '0';
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process(clk,rstn)
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begin
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if rstn='0' then addr_i<=(others=>'0');
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data_i<=(others=>'0');
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elsif rising_edge(clk) then
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if trigger='1' then
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addr_i<=addr;
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data_i<=data;
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end if;
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end if;
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end process;
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process(clk,rstn)
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begin
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if rstn='0' then state<=idle;
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sen_i<='1';
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busy_i<='0';
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sclk_flag<='0';
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elsif rising_edge(clk) then
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case state is
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when idle =>
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if trigger='1' then
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state<=start;
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busy_i<='1';
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else
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state<=idle;
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end if;
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when start =>
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state<=wr_addr;
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when wr_addr =>
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sclk_flag<='1';
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sen_i<='0';
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if bit_count=x"8" then
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state<=wr_data;
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else
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state<=wr_addr;
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end if;
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when wr_data =>
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if bit_count=x"8" then
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state<=done;
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else
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state<=wr_data;
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end if;
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when done =>
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if sclk_r='1' then state<=idle;
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sen_i<='1';
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sclk_flag<='0';
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busy_i<='0';
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else
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state<=done;
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end if;
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when others=> state<=idle;
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end case;
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end if;
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end process;
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sen<=sen_i;
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busy<=busy_i;
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process(clk,rstn)
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begin
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if rstn='0' then
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freq_div<=(others=>'0');
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elsif rising_edge(clk) then
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if sclk_flag='1' then
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if freq_div=x"9" then
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freq_div<=(others=>'0');
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else
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freq_div<=freq_div+'1';
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end if;
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else
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freq_div<=(others=>'0');
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end if;
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end if;
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end process;
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process(clk,rstn)
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begin
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if rstn='0' then
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sclk_r<='0';
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sclk_f<='0';
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elsif rising_edge(clk) then
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sclk_r<='0';
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sclk_f<='0';
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if sclk_flag='1' then
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if freq_div=x"0" then
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sclk_r<='1';
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elsif freq_div=x"5" then
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sclk_f<='1';
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end if;
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end if;
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end if;
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end process;
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process(clk,rstn)
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begin
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if rstn='0' then
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sclk_i<='1';
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elsif rising_edge(clk) then
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if sclk_flag='1' then
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if sclk_r='1' then
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sclk_i<='1';
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elsif sclk_f='1' then
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sclk_i<='0';
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else
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sclk_i<=sclk_i;
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end if;
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else
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sclk_i<='1';
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end if;
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end if;
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end process;
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sclk<=sclk_i;
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process(clk,rstn)
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begin
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if rstn='0' then
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bit_count<=(others=>'0');
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elsif rising_edge(clk) then
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if bit_count=8 then
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bit_count<=(others=>'0');
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elsif sclk_f='1' then
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bit_count<=bit_count+1;
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else
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bit_count<=bit_count;
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end if;
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end if;
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end process;
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process(clk,rstn)
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begin
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if rstn='0' then
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addr_r<=(others=>'0');
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data_r<=(others=>'0');
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sdata_i<='0';
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elsif rising_edge(clk) then
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if state=start then
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addr_r<=addr_i;
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data_r<=data_i;
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elsif state=wr_addr then
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if sclk_r='1' then
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sdata_i<=addr_r(7);
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addr_r<=addr_r(6 downto 0) & '0';
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else
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sdata_i<=sdata_i;
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addr_r<=addr_r;
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end if;
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elsif state=wr_data then
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if sclk_r='1' then
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sdata_i<=data_r(7);
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data_r<=data_r(6 downto 0) & '0';
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else
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sdata_i<=sdata_i;
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data_r<=data_r;
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end if;
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elsif state=done then
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sdata_i<=sdata_i;
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else
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sdata_i<='0';
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end if;
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end if;
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end process;
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sdata<=sdata_i;
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end Behavioral;
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