63 lines
1.8 KiB
Verilog
63 lines
1.8 KiB
Verilog
//============================================================================================
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/*
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* #Author : sterben(Duan)
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* #LastAuthor : sterben(Duan)
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* #Date : 2019-09-27 00:00:34
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* #lastTime : 2020-01-22 23:54:59
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* #FilePath : src\Driver\DAC_driver\DAC9767_driver\DA9767.v
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* #Description : port:
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*/
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//============================================================================================
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module DA9767 #
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(
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parameter INPUT_WIDTH = 14,
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parameter INPUT_STYLE = "signed",
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parameter ALIGNED_STYLE = "LSB"
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)
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(
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input clk_in,
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input [INPUT_WIDTH - 1 : 0] DA_data,
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output DA_clk,
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output DA_wrt,
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output [13:0] DA_out
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);
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generate if(INPUT_STYLE == "signed") begin : OUTPUT
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if (INPUT_WIDTH < 14) begin
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localparam DATA_WIDTH = 14 - INPUT_WIDTH;
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if (ALIGNED_STYLE == "LSB") begin
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assign DA_out = $signed({{DATA_WIDTH{DA_data[INPUT_WIDTH-1]}},DA_data})
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+ $signed(14'd8192);
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end
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else if(ALIGNED_STYLE == "MSB") begin
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reg [DATA_WIDTH - 1 : 0 ] data_buf = 0;
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assign DA_out = $signed({DA_data,data_buf}) + $signed(14'd8192);
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end
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end
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else begin
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assign DA_out = $signed(DA_data[INPUT_WIDTH - 1 : INPUT_WIDTH - 14]) + $signed(14'd8192);
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end
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end
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else if(INPUT_STYLE == "unsigned") begin
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if (INPUT_WIDTH < 14) begin
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localparam DATA_WIDTH = 14 - INPUT_WIDTH;
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if (ALIGNED_STYLE == "LSB") begin
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assign DA_out = {{DATA_WIDTH{DA_data[INPUT_WIDTH-1]}},DA_data};
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end
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else if(ALIGNED_STYLE == "MSB") begin
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reg [DATA_WIDTH - 1 : 0 ] data_buf = 0;
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assign DA_out = {DA_data,data_buf};
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end
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end
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else begin
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assign DA_out = DA_data[INPUT_WIDTH - 1 : INPUT_WIDTH - 14];
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end
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end
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endgenerate
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assign DA_clk = clk_in;
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assign DA_wrt = clk_in;
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endmodule
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