44 lines
560 B
Verilog
44 lines
560 B
Verilog
module circuit(
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input clk,
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input reset,
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input [7:0] fmin,
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output [11:0] dmout
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);
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wire [11:0] d1;
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wire [11:0] d2;
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wire [7:0] dout;
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wire [7:0] output_xhdl0;
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multiplier I1(
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.clk(clk),
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.reset(reset),
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.input1(fmin),
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.input2(dout),
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.output_xhdl0(output_xhdl0)
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);
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fir I4(
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.clock(clk),
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.reset(reset),
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.data_in(d1),
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.data_out(dmout)
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);
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loop_filter I3(
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.clk(clk),
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.reset(reset),
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.c(output_xhdl0),
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.d1(d1),
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.d2(d2)
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);
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nco I2(
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.clk(clk),
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.reset(reset),
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.din(d2),
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.dout(dout)
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);
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endmodule
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