20 lines
400 B
Verilog
20 lines
400 B
Verilog
module CLK_Sample # (
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parameter PHASE_WIDTH = 32
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) (
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input clk_in,
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input RST,
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input [PHASE_WIDTH-1:0] sample_fre,
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output clk_sample
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);
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reg [PHASE_WIDTH-1:0] addr_r = 0;
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always @(posedge clk_in) begin
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if (RST)
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addr_r <= 32'd0;
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else
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addr_r <= addr_r + sample_fre;
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end
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assign clk_sample = addr_r[PHASE_WIDTH-1];
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endmodule
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