77 lines
1.7 KiB
Verilog
77 lines
1.7 KiB
Verilog
`timescale 1ns / 1ps
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module measure
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(
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input clk_sys,
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input clk_samp,
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input rst_n,
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input mearsure_start,
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input [11:0] AD_data,
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output measure_done_q,
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output [21:0] data_out
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);
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parameter cnt_clear = 22'd255;
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reg clk_samp_buf0;
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reg clk_samp_buf1;
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wire clk_samp_impluse = clk_samp_buf0 & ~clk_samp_buf1;//采样脉冲信号
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wire [21:0] mult_data;
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reg [16:0] cnt;
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reg [39:0] sig_energy;
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reg [21:0] data_out_buf;
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reg measure_en;
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wire measure_done = (cnt == cnt_clear) ? 1'b1:1'b0;
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assign measure_done_q = measure_done;
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always@(posedge clk_sys)
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begin
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clk_samp_buf0 <= clk_samp;
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clk_samp_buf1 <= clk_samp_buf0;
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end
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always@(posedge clk_sys)
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begin
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if(!rst_n)
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begin
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measure_en <= 1'b0;
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end
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else if(mearsure_start)
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measure_en <= 1'b1;
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else if(measure_done)
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measure_en <= 1'b0;
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else
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measure_en <= measure_en;
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end
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always@(posedge clk_sys)
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begin
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if(!rst_n)
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begin
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sig_energy <= 40'd0;
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cnt <= 17'd0;
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data_out_buf <= 22'd0;
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end
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else if(cnt == cnt_clear)
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begin
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sig_energy <= 40'd0;
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data_out_buf <= sig_energy[39:8];
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cnt <= 17'd0;
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end
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else if(clk_samp_impluse && measure_en)
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begin
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cnt <= cnt + 17'd1;
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sig_energy <= sig_energy + mult_data;
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end
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else
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begin
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sig_energy <= sig_energy;
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data_out_buf <= data_out_buf;
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cnt <= cnt;
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end
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end
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mult1 mult1_inst
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(
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.A(AD_data),
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.B(AD_data),
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.P(mult_data),
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.CLK(clk_sys),
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.CE(clk_samp_impluse)
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);
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assign data_out = data_out_buf;
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endmodule
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