119 lines
3.7 KiB
Verilog
119 lines
3.7 KiB
Verilog
`timescale 1ns/1ns
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module RGB888_YCbCr444 (
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//global clock
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input clk, //cmos video pixel clock
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input rst_n, //global reset
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//Image data prepred to be processd
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input per_frame_vsync, //Prepared Image data vsync valid signal
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input per_frame_href, //Prepared Image data href vaild signal
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input [7:0] per_img_red, //Prepared Image red data to be processed
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input [7:0] per_img_green, //Prepared Image green data to be processed
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input [7:0] per_img_blue, //Prepared Image blue data to be processed
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//Image data has been processd
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output post_frame_vsync, //Processed Image data vsync valid signal
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output post_frame_href, //Processed Image data href vaild signal
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output [7:0] post_img_Y, //Processed Image brightness output
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output [7:0] post_img_Cb, //Processed Image blue shading output
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output [7:0] post_img_Cr //Processed Image red shading output
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);
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//--------------------------------------------
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/*********************************************
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//Refer to <OV7725 Camera Module Software Applicaton Note> page 5
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Y = (77 *R + 150*G + 29 *B)>>8
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Cb = (-43*R - 85 *G + 128*B)>>8 + 128
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Cr = (128*R - 107*G - 21 *B)>>8 + 128
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--->
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Y = (77 *R + 150*G + 29 *B)>>8
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Cb = (-43*R - 85 *G + 128*B + 32768)>>8
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Cr = (128*R - 107*G - 21 *B + 32768)>>8
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**********************************************/
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//Step 1
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reg [15:0] img_red_r0, img_red_r1, img_red_r2;
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reg [15:0] img_green_r0, img_green_r1, img_green_r2;
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reg [15:0] img_blue_r0, img_blue_r1, img_blue_r2;
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always@(posedge clk or negedge rst_n) begin
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if(!rst_n) begin
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img_red_r0 <= 0;
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img_red_r1 <= 0;
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img_red_r2 <= 0;
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img_green_r0 <= 0;
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img_green_r1 <= 0;
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img_green_r2 <= 0;
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img_blue_r0 <= 0;
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img_blue_r1 <= 0;
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img_blue_r2 <= 0;
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end
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else begin
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img_red_r0 <= per_img_red * 8'd77;
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img_red_r1 <= per_img_red * 8'd43;
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img_red_r2 <= per_img_red * 8'd128;
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img_green_r0 <= per_img_green * 8'd150;
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img_green_r1 <= per_img_green * 8'd85;
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img_green_r2 <= per_img_green * 8'd107;
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img_blue_r0 <= per_img_blue * 8'd29;
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img_blue_r1 <= per_img_blue * 8'd128;
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img_blue_r2 <= per_img_blue * 8'd21;
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end
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end
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//--------------------------------------------------
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//Step 2
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reg [15:0] img_Y_r0;
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reg [15:0] img_Cb_r0;
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reg [15:0] img_Cr_r0;
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always@(posedge clk or negedge rst_n) begin
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if(!rst_n) begin
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img_Y_r0 <= 0;
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img_Cb_r0 <= 0;
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img_Cr_r0 <= 0;
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end
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else begin
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img_Y_r0 <= img_red_r0 + img_green_r0 + img_blue_r0;
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img_Cb_r0 <= img_blue_r1 - img_red_r1 - img_green_r1 + 16'd32768;
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img_Cr_r0 <= img_red_r2 + img_green_r2 + img_blue_r2 + 16'd32768;
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end
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end
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//--------------------------------------------------
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//Step 3
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reg [7:0] img_Y_r1;
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reg [7:0] img_Cb_r1;
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reg [7:0] img_Cr_r1;
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always@(posedge clk or negedge rst_n) begin
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if(!rst_n) begin
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img_Y_r1 <= 0;
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img_Cb_r1 <= 0;
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img_Cr_r1 <= 0;
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end
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else begin
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img_Y_r1 <= img_Y_r0[15:8];
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img_Cb_r1 <= img_Cb_r0[15:8];
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img_Cr_r1 <= img_Cr_r0[15:8];
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end
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end
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//------------------------------------------
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//lag 3 clocks signal sync
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reg [2:0] per_frame_vsync_r;
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reg [2:0] per_frame_href_r;
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always@(posedge clk or negedge rst_n) begin
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if(!rst_n) begin
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per_frame_vsync_r <= 0;
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per_frame_href_r <= 0;
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end
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else begin
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per_frame_vsync_r <= {per_frame_vsync_r[1:0], per_frame_vsync};
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per_frame_href_r <= {per_frame_href_r[1:0], per_frame_href};
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end
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end
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assign post_frame_vsync = per_frame_vsync_r[2];
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assign post_frame_href = per_frame_href_r[2];
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assign post_img_Y = post_frame_href ? img_Y_r1 : 8'd0;
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assign post_img_Cb = post_frame_href ? img_Cb_r1: 8'd0;
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assign post_img_Cr = post_frame_href ? img_Cr_r1: 8'd0;
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endmodule
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