196 lines
8.5 KiB
VHDL
196 lines
8.5 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_unsigned.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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library UNISIM;
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use UNISIM.VComponents.all;
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entity ADC_CFG is
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Port (
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clk : in std_logic;
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rstn : in std_logic;
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sclk : out std_logic;
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sdata : out std_logic;
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sen : out std_logic;
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adc_rst : out std_logic;
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cfg_done : out std_logic
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);
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end ADC_CFG;
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architecture Behavioral of ADC_CFG iimage.pngsimage.png
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image.png
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component CFG_INT
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Port (
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CLK : in STD_LOGIC;--100mhz
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RSTn : in STD_LOGIC;
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TRIG : in STD_LOGIC;
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ADDR : in STD_LOGIC_VECTOR (7 downto 0);
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DATA : in STD_LOGIC_VECTOR (7 downto 0);
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SCLK : out STD_LOGIC;
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SDATA : out STD_LOGIC;
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SEN : out STD_LOGIC;
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BUSY : out STD_LOGIC
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);
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end component;
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type array_reg is array (0 to 25) of std_logic_vector(7 downto 0);
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signal addr_reg : array_reg :=( x"42", --
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x"00", --bit0 readout ; --bit1 reset
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x"01",
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x"03",
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x"25",
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x"29",
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x"2b",
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x"3d",
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x"3f",
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x"40",
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x"41",
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x"42",
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x"45",
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x"4a",
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x"58",
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x"bf",
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x"c1",
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x"cf",
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x"ef",
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x"f1",
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x"f2",
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x"02",
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x"d5",
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x"d7",
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x"db",
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x"00" --the last byte no meaning
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);
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constant data_reg : array_reg :=( x"08", --
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x"00", --bit0 readout ; --bit1 reset
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x"00",
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x"03",
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x"00",
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x"00",
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x"00",
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x"00",
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x"00",
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x"00",
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x"03",
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x"08",
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x"00",
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x"01",
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x"01",
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x"00",
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x"00",
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x"00",
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x"00",
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x"03",
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x"00",
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x"40",
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x"18",
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x"0c",
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x"20",
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x"00" --the last byte no meaning
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);
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signal trig : std_logic;
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signal busy : std_logic;
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signal busy_r : std_logic;
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signal busy_rr : std_logic;
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signal busy_rrr : std_logic;
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signal resetn : std_logic;
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signal busy_pulse : std_logic;
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signal cfg_done_i : std_logic;
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signal byte_count : std_logic_vector(7 downto 0);
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signal addr : std_logic_vector(7 downto 0);
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signal data : std_logic_vector(7 downto 0);
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signal rst_count : std_logic_vector(11 downto 0);
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signal clkIbuf : std_logic;
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signal clkIbufG : std_logic;
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begin
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clkIbufG <= clk;
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CFG_INT_inst : CFG_INT
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Port map(
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CLK => clkIbufG ,--: in STD_LOGIC;--100mhz
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RSTn => rstn ,--: in STD_LOGIC;
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TRIG => trig ,--: in STD_LOGIC;
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ADDR => addr ,--: in STD_LOGIC_VECTOR (7 downto 0);
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DATA => data ,--: in STD_LOGIC_VECTOR (7 downto 0);
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SCLK => sclk ,--: out STD_LOGIC;
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SDATA => sdata ,--: out STD_LOGIC;
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SEN => sen ,--: out STD_LOGIC;
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BUSY => busy --: out STD_LOGIC
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);
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process(clkIbufG,rstn)
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begin
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if rstn='0' then
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rst_count<=(others=>'0');
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elsif rising_edge(clkIbufG) then
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if rst_count=x"2ff" then
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rst_count<=rst_count;
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else
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rst_count<=rst_count+1;
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end if;
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end if;
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end process;
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adc_rst<=not rst_count(9);
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resetn<='1' when rstn='1' and rst_count(9)='1' else '0';
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process(clkIbufG,resetn)
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begin
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if resetn='0' then busy_r<='0';
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busy_rr<='0';
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busy_rrr<='0';
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elsif rising_edge(clkIbufG) then
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busy_r<=busy;
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busy_rr<=busy_r;
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busy_rrr<=busy_rr;
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end if;
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end process;
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busy_pulse<='1' when busy_r='0' and busy_rr='1' else '0';
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process(clkIbufG,resetn)
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begin
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if resetn='0' then byte_count<=(others=>'0');
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cfg_done_i<='0';
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elsif rising_edge(clkIbufG) then
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cfg_done_i<='0';
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if byte_count=x"10" then
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byte_count<=byte_count;
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cfg_done_i<='1';
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elsif busy_pulse='1' then
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byte_count<=byte_count+1;
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else
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byte_count<=byte_count;
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end if;
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end if;
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end process;
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cfg_done<=cfg_done_i;
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addr<=addr_reg(conv_integer(byte_count));
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data<=data_reg(conv_integer(byte_count));
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process(clkIbufG,resetn)
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begin
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if resetn='0' then
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trig<='0';
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elsif rising_edge(clkIbufG) then
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if byte_count/=x"10" and busy_rrr='0' then
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trig<='1';
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else
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trig<='0';
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end if;
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end if;
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end process;
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end Behavioral;
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