52 lines
1.2 KiB
Verilog
52 lines
1.2 KiB
Verilog
`timescale 1ns / 1ps
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module ADS412x_driver(
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// input sys_rst_n,
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input user_clk,
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output [11:0] user_rd_data,
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output adc_sclk, // sclk
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output adc_sdata, // sda
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output adc_reset,
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output adc_sen,
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input [11:0] adc_data,
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input adc_clk,
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output adc_samp_clk
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);
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wire sys_rst_n;
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assign sys_rst_n = 1;
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wire adc_config_done;
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wire rst_n;
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reg [11:0] adc_data_r;
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reg [11:0] adc_data_rr;
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assign adc_samp_clk=user_clk;
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assign rst_n = ((adc_config_done == 1'b1) && (sys_rst_n == 1'b1)) ? 1'b1 : 1'b0;
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assign user_rd_data=adc_data_rr;////
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ADC_CFG u_ADS4128_CFG(
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.clk ( user_clk ),
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.rstn ( sys_rst_n ),
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.sclk ( adc_sclk ),
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.sdata ( adc_sdata ),
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.sen ( adc_sen ),
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.adc_rst ( adc_reset ),
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.cfg_done ( adc_config_done )
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);
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always @ (posedge adc_clk) begin
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if (rst_n == 1'b0) begin
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adc_data_r <= 12'h000;
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adc_data_rr <= 12'h000;
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end
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else begin
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adc_data_r <= adc_data;
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adc_data_rr <= adc_data_r + 12'b1000_0000_0000;
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end
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end
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endmodule
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