35 lines
746 B
Verilog
35 lines
746 B
Verilog
module DAC_PWM #
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(
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parameter MAIN_FRE = 500,
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parameter PWM_FRE = 1000,
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parameter PHASE_WIDTH = 32
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)
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(
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input clk_in,
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input RST,
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output DAC_PWM,
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input [PHASE_WIDTH-1:0] data_in
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);
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localparam [PHASE_WIDTH-1:0] DC_ADD = (2**(PHASE_WIDTH-1)) - 1;
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localparam [PHASE_WIDTH-1:0] FRE_WORD = (2**PHASE_WIDTH)*PWM_FRE/(MAIN_FRE*1000);
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reg [PHASE_WIDTH-1:0] addr_r = 0;
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always @(posedge clk_in) begin
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if (RST)
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addr_r <= 0;
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else
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addr_r <= addr_r + FRE_WORD;
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end
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reg [PHASE_WIDTH-1:0] duty_r = 0;
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always @(posedge clk_in) begin
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if (RST)
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duty_r <= 32'd0;
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else
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duty_r <= $signed(data_in) + DC_ADD;
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end
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assign DAC_PWM = (addr_r <= duty_r) ? 1'b1 : 1'b0;
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endmodule |