112 lines
2.6 KiB
Verilog
112 lines
2.6 KiB
Verilog
/********************************************
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wire Motor_Control;
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Motor_driver Motor_driver_u(
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.clk_in(clk_50m),
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.rst_n(1'd1),
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.Trig(Trig),
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.Meter(16'd4),
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.Motor_Control(Motor_Control)
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);
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********************************************/
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module Motor_driver (
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input clk_in,
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input rst_n,
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input Trig,
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input [15:0] Meter,
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output reg Motor_Control
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);
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parameter MAIN_FRE = 50000000;
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parameter MOTOR_FRE = 1000;
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parameter SET_TIME = MAIN_FRE/MOTOR_FRE/2;
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/***************************************************/
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//define the data lock
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reg Trig_SIG = 0;
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reg Trig_SIG_buf = 0;
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wire Trig_SIG_pose = Trig_SIG & ~Trig_SIG_buf;
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wire Trig_SIG_nege = ~Trig_SIG & Trig_SIG_buf;
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always@(posedge clk_in) begin
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Trig_SIG <= Trig;
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Trig_SIG_buf <= Trig_SIG;
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end
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/***************************************************/
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/***************************************************/
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//define the time counter
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reg [15:0] cnt0 = 0;
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reg Motor_Control_r = 0;
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always@(posedge clk_in) begin
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if (cnt0 == SET_TIME) begin
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cnt0 <= 15'd0;
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Motor_Control_r <= ~Motor_Control_r;
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end
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else
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cnt0 <= cnt0 + 1'd1;
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end
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/***************************************************/
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/***************************************************/
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//define the data lock
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reg motor_sig = 0;
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reg motor_sig_buf = 0;
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wire motor_sig_pose = motor_sig & ~motor_sig_buf;
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wire motor_sig_nege = ~motor_sig & motor_sig_buf;
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always@(posedge clk_in) begin
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motor_sig <= Motor_Control_r;
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motor_sig_buf <= motor_sig;
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end
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/***************************************************/
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/***************************************************/
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//define the time counter
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reg [15:0] cnt1 = 0;
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reg CNT_CE = 0;
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always@(posedge clk_in) begin
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if (Trig_SIG_pose) begin
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CNT_CE <= 1'd1;
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end
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else if(cnt1 == Meter) begin
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if (motor_sig_nege) begin
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CNT_CE <= 1'd0;
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end
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else begin
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CNT_CE <= CNT_CE;
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end
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end
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else begin
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CNT_CE <= CNT_CE;
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end
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end
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/***************************************************/
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reg MOTOR_CE = 0;
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always @(posedge clk_in) begin
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if (CNT_CE) begin
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if (motor_sig_pose) begin
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cnt1 <= cnt1 + 1'd1; //cnt1 counter = cnt1 counter + 1
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MOTOR_CE <= 1'd1;
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end
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else begin
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MOTOR_CE <= MOTOR_CE;
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end
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end
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else begin
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cnt1 <= 16'd0;
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MOTOR_CE <= 1'd0;
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end
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end
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always @(*) begin
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case (MOTOR_CE)
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1'b0 : begin Motor_Control <= 1'b0; end
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1'b1 : begin Motor_Control <= Motor_Control_r; end
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default : begin Motor_Control <= 1'b0; end
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endcase
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end
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endmodule |