111 lines
3.4 KiB
Verilog
111 lines
3.4 KiB
Verilog
module uart_tx_control
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(
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input clk_50m,
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input rst_n,
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input uart_tx_done,
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input start_sig,
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input [31:0] uart_data_a,
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input [31:0] uart_data_b,
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input [1:0] mod,
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output [7:0] uart_tx_data,
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output tx_sig_q,
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output uart_tx_en
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);
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parameter clk_pw_div_1 = 16'd44999;
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parameter clk_pw_div_2 = 16'd249999;
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reg [4:0] state;
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reg [7:0] uart_tx_data_r;
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reg tx_en_r;
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reg tx_sig;
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reg [31:0] uart_data_a_buf;
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reg [31:0] uart_data_b_buf;
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reg start_sig_buf;
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reg [2:0] state_sweep;
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reg [2:0] state_piont;
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reg [22:0] clk_cnt;
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always@(posedge clk_50m or negedge rst_n)
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begin
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if(!rst_n)
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begin
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start_sig_buf <= 1'd0;
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state_sweep <= 3'd0;
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state_piont <= 3'd0;
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clk_cnt <= 23'd0;
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end
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else if(mod == 2'b01)//扫频
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begin
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state_piont <= 3'd0;
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case(state_sweep)
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3'd0:begin start_sig_buf<=1'd0; clk_cnt<=15'd0; state_sweep<=3'd1;end
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3'd1:begin if(start_sig) state_sweep<=2'd2;end
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3'd2:begin if(clk_cnt==clk_pw_div_1) state_sweep<=3'd3; else clk_cnt<=clk_cnt+23'd1;end
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3'd3:begin start_sig_buf<=1'd1; state_sweep<=3'd0; end
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endcase
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end
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else if(mod == 2'b10)//点频
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begin
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state_sweep <= 3'd0;
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case(state_piont)
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3'd0:begin start_sig_buf<=1'd0; clk_cnt<=15'd0; state_piont<=3'd1;end
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3'd1:begin if(start_sig) state_piont<=2'd2;end
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3'd2:begin start_sig_buf<=1'd0; if(clk_cnt==clk_pw_div_2) state_piont<=3'd3; else clk_cnt<=clk_cnt+23'd1;end
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3'd3:begin start_sig_buf<=1'd1; clk_cnt<=15'd0; state_piont<=3'd2; end
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endcase
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end
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else
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begin
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start_sig_buf <= 1'd0;
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state_sweep <= 3'd0;
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state_piont <= 3'd0;
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clk_cnt <= 15'd0;
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end
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end
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always@(posedge clk_50m or negedge rst_n)
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begin
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if(!rst_n)
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begin
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uart_data_a_buf <= 28'd0;
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uart_data_b_buf <= 28'd0;
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end
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else if(start_sig_buf)
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begin
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uart_data_a_buf <= uart_data_a;
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uart_data_b_buf <= uart_data_b;
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end
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end
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always@(posedge clk_50m or negedge rst_n)
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begin
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if(!rst_n)
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begin
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state <= 5'd0;
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tx_sig <= 1'd0;
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uart_tx_data_r <= 8'd0;
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tx_en_r <= 1'd0;
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end
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else
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begin
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case(state)
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5'd0:begin if(start_sig_buf)begin state<=state+1; tx_sig<=0; tx_en_r<=1; end end
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5'd1:begin uart_tx_data_r<=8'h99; tx_en_r<=1; state<=state+1; end
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5'd2:begin if(uart_tx_done) begin uart_tx_data_r<=8'h24; tx_en_r<=1; state<=state+1; end end
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5'd3:begin if(uart_tx_done) begin uart_tx_data_r<=uart_data_a_buf[7:0]; tx_en_r<=1; state<=state+1; end end
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5'd4:begin if(uart_tx_done) begin uart_tx_data_r<=uart_data_a_buf[15:8]; tx_en_r<=1; state<=state+1; end end
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5'd5:begin if(uart_tx_done) begin uart_tx_data_r<=uart_data_a_buf[23:16]; tx_en_r<=1; state<=state+1; end end
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5'd6:begin if(uart_tx_done) begin uart_tx_data_r<=uart_data_a_buf[31:24]; tx_en_r<=1; state<=state+1; end end
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5'd7:begin if(uart_tx_done) begin uart_tx_data_r<=uart_data_b_buf[7:0]; tx_en_r<=1; state<=state+1; end end
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5'd8:begin if(uart_tx_done) begin uart_tx_data_r<=uart_data_b_buf[15:8]; tx_en_r<=1; state<=state+1; end end
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5'd9:begin if(uart_tx_done) begin uart_tx_data_r<=uart_data_b_buf[23:16]; tx_en_r<=1; state<=state+1; end end
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5'd10:begin if(uart_tx_done) begin uart_tx_data_r<=uart_data_b_buf[31:24]; tx_en_r<=1; state<=state+1; end end
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5'd11:begin tx_en_r<=0; state<=state+1; end
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5'd12:begin if(uart_tx_done) begin tx_sig<=1; state<=5'd0;end end
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default:begin state <= 0; end
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endcase
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end
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end
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assign uart_tx_data = uart_tx_data_r;
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assign uart_tx_en = tx_en_r;
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assign tx_sig_q = tx_sig;
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endmodule
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