33 lines
682 B
Verilog
33 lines
682 B
Verilog
module Line_Shift_RAM #(
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parameter RAM_Length = 640, //640*480
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parameter DATA_WIDTH = 8
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) (
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input clken,
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input clock,
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input [DATA_WIDTH-1:0] shiftin,
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output [DATA_WIDTH-1:0] taps0x,
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output [DATA_WIDTH-1:0] taps1x
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);
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RAMshift_taps #(
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.TOTAL_RAM_Length (RAM_Length),
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.DATA_WIDTH (DATA_WIDTH)
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) RAMshfit_taps_u1 (
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.clken(clken),
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.clock(clock),
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.Delay_Length(RAM_Length),
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.shiftin(shiftin),
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.shiftout(taps0x)
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);
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RAMshift_taps #(
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.TOTAL_RAM_Length (RAM_Length),
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.DATA_WIDTH (DATA_WIDTH)
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) RAMshfit_taps_u2 (
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.clken(clken),
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.clock(clock),
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.Delay_Length(RAM_Length),
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.shiftin(taps0x),
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.shiftout(taps1x)
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);
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endmodule |