2261 lines
66 KiB
Plaintext
2261 lines
66 KiB
Plaintext
{
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"design": {
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"design_info": {
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"boundary_crc": "0x499C68C943DC87C8",
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"name": "PCIe_Test",
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"synth_flow_mode": "Hierarchical",
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"validated": "true"
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},
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"design_tree": {
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"processing_system7_0": "",
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"axi_pcie_0": "",
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"xlconstant_0": "",
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"proc_sys_reset_0": "",
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"proc_sys_reset_1": "",
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"axi_cdma_0": "",
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"xlconcat_0": "",
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"axi_interconnect_0": {
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"xbar": "",
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"s00_couplers": {},
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"s01_couplers": {},
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"m00_couplers": {
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"auto_ds": "",
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"auto_pc": ""
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}
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},
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"axi_interconnect_1": {
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"xbar": "",
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"s00_couplers": {
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"auto_pc": "",
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"auto_us": ""
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},
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"s01_couplers": {},
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"m00_couplers": {},
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"m01_couplers": {
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"auto_cc": "",
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"auto_ds": "",
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"auto_pc": ""
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},
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"m02_couplers": {
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"auto_ds": "",
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"auto_pc": ""
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}
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},
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"axi_interconnect_2": {
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"xbar": "",
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"s00_couplers": {},
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"m00_couplers": {},
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"m01_couplers": {}
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}
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},
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"interface_ports": {
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"DDR": {
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"mode": "Master",
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"vlnv": "xilinx.com:interface:ddrx_rtl:1.0",
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"parameters": {
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"AXI_ARBITRATION_SCHEME": {
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"value": "TDM",
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"value_src": "default"
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},
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"BURST_LENGTH": {
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"value": "8",
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"value_src": "default"
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},
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"CAN_DEBUG": {
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"value": "false",
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"value_src": "default"
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},
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"CAS_LATENCY": {
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"value": "11",
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"value_src": "default"
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},
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"CAS_WRITE_LATENCY": {
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"value": "11",
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"value_src": "default"
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},
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"CS_ENABLED": {
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"value": "true",
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"value_src": "default"
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},
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"DATA_MASK_ENABLED": {
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"value": "true",
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"value_src": "default"
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},
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"DATA_WIDTH": {
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"value": "8",
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"value_src": "default"
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},
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"MEMORY_TYPE": {
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"value": "COMPONENTS",
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"value_src": "default"
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},
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"MEM_ADDR_MAP": {
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"value": "ROW_COLUMN_BANK",
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"value_src": "default"
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},
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"SLOT": {
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"value": "Single",
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"value_src": "default"
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},
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"TIMEPERIOD_PS": {
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"value": "1250",
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"value_src": "default"
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}
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}
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},
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"FIXED_IO": {
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"mode": "Master",
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"vlnv": "xilinx.com:display_processing_system7:fixedio_rtl:1.0",
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"parameters": {
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"CAN_DEBUG": {
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"value": "false",
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"value_src": "default"
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}
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}
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},
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"pcie_7x_mgt": {
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"mode": "Master",
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"vlnv": "xilinx.com:interface:pcie_7x_mgt_rtl:1.0"
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}
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},
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"ports": {
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"perst": {
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"type": "rst",
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"direction": "O",
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"left": "0",
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"right": "0",
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"parameters": {
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"INSERT_VIP": {
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"value": "0",
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"value_src": "default"
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},
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"POLARITY": {
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"value": "ACTIVE_HIGH",
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"value_src": "const_prop"
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}
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}
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}
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},
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"components": {
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"processing_system7_0": {
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"vlnv": "xilinx.com:ip:processing_system7:5.5",
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"xci_name": "zynq_default_processing_system7_0_0",
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"parameters": {
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"PCW_ACT_APU_PERIPHERAL_FREQMHZ": {
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"value": "666.666687"
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},
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"PCW_ACT_CAN_PERIPHERAL_FREQMHZ": {
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"value": "10.000000"
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},
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"PCW_ACT_DCI_PERIPHERAL_FREQMHZ": {
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"value": "10.158730"
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},
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"PCW_ACT_ENET0_PERIPHERAL_FREQMHZ": {
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"value": "10.000000"
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},
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"PCW_ACT_ENET1_PERIPHERAL_FREQMHZ": {
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"value": "10.000000"
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},
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"PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ": {
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"value": "100.000000"
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},
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"PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ": {
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"value": "250.000000"
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},
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"PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ": {
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"value": "10.000000"
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},
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"PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ": {
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"value": "10.000000"
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},
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"PCW_ACT_PCAP_PERIPHERAL_FREQMHZ": {
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"value": "200.000000"
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},
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"PCW_ACT_QSPI_PERIPHERAL_FREQMHZ": {
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"value": "10.000000"
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},
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"PCW_ACT_SDIO_PERIPHERAL_FREQMHZ": {
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"value": "10.000000"
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},
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"PCW_ACT_SMC_PERIPHERAL_FREQMHZ": {
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"value": "10.000000"
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},
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"PCW_ACT_SPI_PERIPHERAL_FREQMHZ": {
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"value": "10.000000"
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},
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"PCW_ACT_TPIU_PERIPHERAL_FREQMHZ": {
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"value": "200.000000"
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},
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"PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ": {
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"value": "111.111115"
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},
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"PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ": {
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"value": "111.111115"
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},
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"PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ": {
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"value": "111.111115"
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},
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"PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ": {
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"value": "111.111115"
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},
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"PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ": {
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"value": "111.111115"
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},
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"PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ": {
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"value": "111.111115"
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},
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"PCW_ACT_UART_PERIPHERAL_FREQMHZ": {
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"value": "100.000000"
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},
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"PCW_ACT_WDT_PERIPHERAL_FREQMHZ": {
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"value": "111.111115"
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},
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"PCW_CLK0_FREQ": {
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"value": "100000000"
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},
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"PCW_CLK1_FREQ": {
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"value": "250000000"
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},
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"PCW_CLK2_FREQ": {
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"value": "10000000"
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},
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"PCW_CLK3_FREQ": {
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"value": "10000000"
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},
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"PCW_DDR_RAM_HIGHADDR": {
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"value": "0x3FFFFFFF"
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},
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"PCW_ENET0_PERIPHERAL_CLKSRC": {
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"value": "IO PLL"
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},
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"PCW_ENET0_PERIPHERAL_ENABLE": {
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"value": "0"
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},
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"PCW_EN_CLK0_PORT": {
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"value": "1"
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},
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"PCW_EN_CLK1_PORT": {
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"value": "1"
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},
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"PCW_EN_CLKTRIG0_PORT": {
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"value": "0"
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},
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"PCW_EN_EMIO_ENET0": {
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"value": "0"
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},
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"PCW_EN_EMIO_GPIO": {
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"value": "0"
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},
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"PCW_EN_EMIO_UART0": {
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"value": "0"
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},
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"PCW_EN_ENET0": {
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"value": "0"
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},
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"PCW_EN_QSPI": {
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"value": "0"
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},
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"PCW_EN_RST0_PORT": {
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"value": "1"
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},
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"PCW_EN_SDIO0": {
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"value": "0"
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},
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"PCW_EN_UART0": {
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"value": "1"
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},
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"PCW_EN_UART1": {
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"value": "0"
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},
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"PCW_FCLK_CLK0_BUF": {
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"value": "FALSE"
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},
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"PCW_FCLK_CLK1_BUF": {
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"value": "TRUE"
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},
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"PCW_FPGA0_PERIPHERAL_FREQMHZ": {
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"value": "100"
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},
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"PCW_FPGA1_PERIPHERAL_FREQMHZ": {
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"value": "250"
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},
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"PCW_FPGA_FCLK0_ENABLE": {
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"value": "1"
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},
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"PCW_FPGA_FCLK1_ENABLE": {
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"value": "1"
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},
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"PCW_GPIO_EMIO_GPIO_ENABLE": {
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"value": "0"
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},
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"PCW_IRQ_F2P_INTR": {
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"value": "1"
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},
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"PCW_MIO_14_IOTYPE": {
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"value": "LVCMOS 3.3V"
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},
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"PCW_MIO_14_PULLUP": {
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"value": "enabled"
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},
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"PCW_MIO_14_SLEW": {
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"value": "slow"
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},
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"PCW_MIO_15_IOTYPE": {
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"value": "LVCMOS 3.3V"
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},
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"PCW_MIO_15_PULLUP": {
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"value": "enabled"
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},
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"PCW_MIO_15_SLEW": {
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"value": "slow"
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},
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"PCW_MIO_TREE_PERIPHERALS": {
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"value": "unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#UART 0#UART 0#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned"
|
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},
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|
"PCW_MIO_TREE_SIGNALS": {
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|
"value": "unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#rx#tx#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned"
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},
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"PCW_NAND_PERIPHERAL_ENABLE": {
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"value": "0"
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},
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"PCW_NOR_PERIPHERAL_ENABLE": {
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"value": "0"
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},
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"PCW_PRESET_BANK1_VOLTAGE": {
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"value": "LVCMOS 1.8V"
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},
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"PCW_QSPI_PERIPHERAL_ENABLE": {
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"value": "0"
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},
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"PCW_SD0_PERIPHERAL_ENABLE": {
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"value": "0"
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},
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"PCW_SDIO_PERIPHERAL_VALID": {
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"value": "0"
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|
},
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|
"PCW_UART0_GRP_FULL_ENABLE": {
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"value": "0"
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|
},
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"PCW_UART0_PERIPHERAL_ENABLE": {
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"value": "1"
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},
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"PCW_UART0_UART0_IO": {
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"value": "MIO 14 .. 15"
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},
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"PCW_UART1_PERIPHERAL_ENABLE": {
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"value": "0"
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},
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"PCW_UART_PERIPHERAL_FREQMHZ": {
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"value": "100"
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},
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"PCW_UART_PERIPHERAL_VALID": {
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"value": "1"
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},
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|
"PCW_UIPARAM_ACT_DDR_FREQ_MHZ": {
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"value": "533.333374"
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|
},
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|
"PCW_UIPARAM_DDR_PARTNO": {
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|
"value": "MT41J256M16 RE-125"
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},
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|
"PCW_USE_FABRIC_INTERRUPT": {
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"value": "1"
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|
},
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|
"PCW_USE_M_AXI_GP0": {
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|
"value": "1"
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|
},
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|
"PCW_USE_S_AXI_HP0": {
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"value": "1"
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|
}
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|
}
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},
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|
"axi_pcie_0": {
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"vlnv": "xilinx.com:ip:axi_pcie:2.9",
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"xci_name": "zynq_default_axi_pcie_0_0",
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"parameters": {
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"BAR0_SCALE": {
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"value": "Gigabytes"
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},
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"BAR0_SIZE": {
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"value": "1"
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},
|
|
"BASEADDR": {
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"value": "0x00000000"
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},
|
|
"BASE_CLASS_MENU": {
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"value": "Bridge_device"
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|
},
|
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"CLASS_CODE": {
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"value": "0x060400"
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},
|
|
"DEVICE_ID": {
|
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"value": "0x7124"
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},
|
|
"HIGHADDR": {
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"value": "0x001FFFFF"
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},
|
|
"INCLUDE_RC": {
|
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"value": "Root_Port_of_PCI_Express_Root_Complex"
|
|
},
|
|
"MAX_LINK_SPEED": {
|
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"value": "5.0_GT/s"
|
|
},
|
|
"M_AXI_DATA_WIDTH": {
|
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"value": "128"
|
|
},
|
|
"NO_OF_LANES": {
|
|
"value": "X4"
|
|
},
|
|
"REF_CLK_FREQ": {
|
|
"value": "100_MHz"
|
|
},
|
|
"SLOT_CLOCK_CONFIG": {
|
|
"value": "false"
|
|
},
|
|
"SUB_CLASS_INTERFACE_MENU": {
|
|
"value": "InfiniBand_to_PCI_host_bridge"
|
|
},
|
|
"S_AXI_DATA_WIDTH": {
|
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"value": "128"
|
|
}
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|
}
|
|
},
|
|
"xlconstant_0": {
|
|
"vlnv": "xilinx.com:ip:xlconstant:1.1",
|
|
"xci_name": "zynq_default_xlconstant_0_0",
|
|
"parameters": {
|
|
"CONST_VAL": {
|
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"value": "0"
|
|
}
|
|
}
|
|
},
|
|
"proc_sys_reset_0": {
|
|
"vlnv": "xilinx.com:ip:proc_sys_reset:5.0",
|
|
"xci_name": "zynq_default_proc_sys_reset_0_0"
|
|
},
|
|
"proc_sys_reset_1": {
|
|
"vlnv": "xilinx.com:ip:proc_sys_reset:5.0",
|
|
"xci_name": "zynq_default_proc_sys_reset_0_1"
|
|
},
|
|
"axi_cdma_0": {
|
|
"vlnv": "xilinx.com:ip:axi_cdma:4.1",
|
|
"xci_name": "zynq_default_axi_cdma_0_0",
|
|
"parameters": {
|
|
"C_INCLUDE_DRE": {
|
|
"value": "0"
|
|
},
|
|
"C_INCLUDE_SF": {
|
|
"value": "0"
|
|
},
|
|
"C_INCLUDE_SG": {
|
|
"value": "0"
|
|
},
|
|
"C_M_AXI_DATA_WIDTH": {
|
|
"value": "128"
|
|
},
|
|
"C_M_AXI_MAX_BURST_LEN": {
|
|
"value": "4"
|
|
},
|
|
"C_USE_DATAMOVER_LITE": {
|
|
"value": "0"
|
|
}
|
|
}
|
|
},
|
|
"xlconcat_0": {
|
|
"vlnv": "xilinx.com:ip:xlconcat:2.1",
|
|
"xci_name": "zynq_default_xlconcat_0_0"
|
|
},
|
|
"axi_interconnect_0": {
|
|
"vlnv": "xilinx.com:ip:axi_interconnect:2.1",
|
|
"xci_name": "zynq_default_axi_interconnect_0_0",
|
|
"parameters": {
|
|
"NUM_MI": {
|
|
"value": "1"
|
|
},
|
|
"NUM_SI": {
|
|
"value": "2"
|
|
}
|
|
},
|
|
"interface_ports": {
|
|
"S00_AXI": {
|
|
"mode": "Slave",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
},
|
|
"M00_AXI": {
|
|
"mode": "Master",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
},
|
|
"S01_AXI": {
|
|
"mode": "Slave",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
}
|
|
},
|
|
"ports": {
|
|
"ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_RESET": {
|
|
"value": "ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
},
|
|
"S00_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "S00_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "S00_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"S00_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
},
|
|
"M00_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "M00_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "M00_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"M00_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
},
|
|
"S01_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "S01_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "S01_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"S01_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
}
|
|
},
|
|
"components": {
|
|
"xbar": {
|
|
"vlnv": "xilinx.com:ip:axi_crossbar:2.1",
|
|
"xci_name": "zynq_default_xbar_0",
|
|
"parameters": {
|
|
"NUM_MI": {
|
|
"value": "1"
|
|
},
|
|
"NUM_SI": {
|
|
"value": "2"
|
|
},
|
|
"STRATEGY": {
|
|
"value": "0"
|
|
}
|
|
}
|
|
},
|
|
"s00_couplers": {
|
|
"interface_ports": {
|
|
"M_AXI": {
|
|
"mode": "Master",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
},
|
|
"S_AXI": {
|
|
"mode": "Slave",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
}
|
|
},
|
|
"ports": {
|
|
"M_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "M_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "M_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"M_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
},
|
|
"S_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "S_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "S_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"S_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
}
|
|
},
|
|
"interface_nets": {
|
|
"s00_couplers_to_s00_couplers": {
|
|
"interface_ports": [
|
|
"S_AXI",
|
|
"M_AXI"
|
|
]
|
|
}
|
|
}
|
|
},
|
|
"s01_couplers": {
|
|
"interface_ports": {
|
|
"M_AXI": {
|
|
"mode": "Master",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
},
|
|
"S_AXI": {
|
|
"mode": "Slave",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
}
|
|
},
|
|
"ports": {
|
|
"M_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "M_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "M_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"M_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
},
|
|
"S_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "S_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "S_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"S_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
}
|
|
},
|
|
"interface_nets": {
|
|
"s01_couplers_to_s01_couplers": {
|
|
"interface_ports": [
|
|
"S_AXI",
|
|
"M_AXI"
|
|
]
|
|
}
|
|
}
|
|
},
|
|
"m00_couplers": {
|
|
"interface_ports": {
|
|
"M_AXI": {
|
|
"mode": "Master",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
},
|
|
"S_AXI": {
|
|
"mode": "Slave",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
}
|
|
},
|
|
"ports": {
|
|
"M_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "M_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "M_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"M_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
},
|
|
"S_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "S_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "S_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"S_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
}
|
|
},
|
|
"components": {
|
|
"auto_ds": {
|
|
"vlnv": "xilinx.com:ip:axi_dwidth_converter:2.1",
|
|
"xci_name": "zynq_default_auto_ds_0",
|
|
"parameters": {
|
|
"MAX_SPLIT_BEATS": {
|
|
"value": "16"
|
|
},
|
|
"MI_DATA_WIDTH": {
|
|
"value": "64"
|
|
},
|
|
"SI_DATA_WIDTH": {
|
|
"value": "128"
|
|
}
|
|
}
|
|
},
|
|
"auto_pc": {
|
|
"vlnv": "xilinx.com:ip:axi_protocol_converter:2.1",
|
|
"xci_name": "zynq_default_auto_pc_0",
|
|
"parameters": {
|
|
"MI_PROTOCOL": {
|
|
"value": "AXI3"
|
|
},
|
|
"SI_PROTOCOL": {
|
|
"value": "AXI4"
|
|
},
|
|
"TRANSLATION_MODE": {
|
|
"value": "0"
|
|
}
|
|
}
|
|
}
|
|
},
|
|
"interface_nets": {
|
|
"m00_couplers_to_auto_ds": {
|
|
"interface_ports": [
|
|
"S_AXI",
|
|
"auto_ds/S_AXI"
|
|
]
|
|
},
|
|
"auto_ds_to_auto_pc": {
|
|
"interface_ports": [
|
|
"auto_ds/M_AXI",
|
|
"auto_pc/S_AXI"
|
|
]
|
|
},
|
|
"auto_pc_to_m00_couplers": {
|
|
"interface_ports": [
|
|
"M_AXI",
|
|
"auto_pc/M_AXI"
|
|
]
|
|
}
|
|
},
|
|
"nets": {
|
|
"S_ACLK_1": {
|
|
"ports": [
|
|
"S_ACLK",
|
|
"auto_ds/s_axi_aclk",
|
|
"auto_pc/aclk"
|
|
]
|
|
},
|
|
"S_ARESETN_1": {
|
|
"ports": [
|
|
"S_ARESETN",
|
|
"auto_ds/s_axi_aresetn",
|
|
"auto_pc/aresetn"
|
|
]
|
|
}
|
|
}
|
|
}
|
|
},
|
|
"interface_nets": {
|
|
"xbar_to_m00_couplers": {
|
|
"interface_ports": [
|
|
"xbar/M00_AXI",
|
|
"m00_couplers/S_AXI"
|
|
]
|
|
},
|
|
"axi_interconnect_0_to_s00_couplers": {
|
|
"interface_ports": [
|
|
"S00_AXI",
|
|
"s00_couplers/S_AXI"
|
|
]
|
|
},
|
|
"s00_couplers_to_xbar": {
|
|
"interface_ports": [
|
|
"s00_couplers/M_AXI",
|
|
"xbar/S00_AXI"
|
|
]
|
|
},
|
|
"axi_interconnect_0_to_s01_couplers": {
|
|
"interface_ports": [
|
|
"S01_AXI",
|
|
"s01_couplers/S_AXI"
|
|
]
|
|
},
|
|
"s01_couplers_to_xbar": {
|
|
"interface_ports": [
|
|
"s01_couplers/M_AXI",
|
|
"xbar/S01_AXI"
|
|
]
|
|
},
|
|
"m00_couplers_to_axi_interconnect_0": {
|
|
"interface_ports": [
|
|
"M00_AXI",
|
|
"m00_couplers/M_AXI"
|
|
]
|
|
}
|
|
},
|
|
"nets": {
|
|
"axi_interconnect_0_ACLK_net": {
|
|
"ports": [
|
|
"ACLK",
|
|
"xbar/aclk",
|
|
"s00_couplers/M_ACLK",
|
|
"s01_couplers/M_ACLK",
|
|
"m00_couplers/S_ACLK"
|
|
]
|
|
},
|
|
"axi_interconnect_0_ARESETN_net": {
|
|
"ports": [
|
|
"ARESETN",
|
|
"xbar/aresetn",
|
|
"s00_couplers/M_ARESETN",
|
|
"s01_couplers/M_ARESETN",
|
|
"m00_couplers/S_ARESETN"
|
|
]
|
|
},
|
|
"S00_ACLK_1": {
|
|
"ports": [
|
|
"S00_ACLK",
|
|
"s00_couplers/S_ACLK"
|
|
]
|
|
},
|
|
"S00_ARESETN_1": {
|
|
"ports": [
|
|
"S00_ARESETN",
|
|
"s00_couplers/S_ARESETN"
|
|
]
|
|
},
|
|
"S01_ACLK_1": {
|
|
"ports": [
|
|
"S01_ACLK",
|
|
"s01_couplers/S_ACLK"
|
|
]
|
|
},
|
|
"S01_ARESETN_1": {
|
|
"ports": [
|
|
"S01_ARESETN",
|
|
"s01_couplers/S_ARESETN"
|
|
]
|
|
},
|
|
"M00_ACLK_1": {
|
|
"ports": [
|
|
"M00_ACLK",
|
|
"m00_couplers/M_ACLK"
|
|
]
|
|
},
|
|
"M00_ARESETN_1": {
|
|
"ports": [
|
|
"M00_ARESETN",
|
|
"m00_couplers/M_ARESETN"
|
|
]
|
|
}
|
|
}
|
|
},
|
|
"axi_interconnect_1": {
|
|
"vlnv": "xilinx.com:ip:axi_interconnect:2.1",
|
|
"xci_name": "zynq_default_axi_interconnect_0_1",
|
|
"parameters": {
|
|
"NUM_MI": {
|
|
"value": "3"
|
|
},
|
|
"NUM_SI": {
|
|
"value": "2"
|
|
}
|
|
},
|
|
"interface_ports": {
|
|
"S00_AXI": {
|
|
"mode": "Slave",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
},
|
|
"M00_AXI": {
|
|
"mode": "Master",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
},
|
|
"S01_AXI": {
|
|
"mode": "Slave",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
},
|
|
"M01_AXI": {
|
|
"mode": "Master",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
},
|
|
"M02_AXI": {
|
|
"mode": "Master",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
}
|
|
},
|
|
"ports": {
|
|
"ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_RESET": {
|
|
"value": "ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
},
|
|
"S00_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "S00_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "S00_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"S00_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
},
|
|
"M00_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "M00_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "M00_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"M00_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
},
|
|
"S01_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "S01_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "S01_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"S01_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
},
|
|
"M01_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "M01_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "M01_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"M01_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
},
|
|
"M02_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "M02_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "M02_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"M02_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
}
|
|
},
|
|
"components": {
|
|
"xbar": {
|
|
"vlnv": "xilinx.com:ip:axi_crossbar:2.1",
|
|
"xci_name": "zynq_default_xbar_1",
|
|
"parameters": {
|
|
"NUM_MI": {
|
|
"value": "3"
|
|
},
|
|
"NUM_SI": {
|
|
"value": "2"
|
|
},
|
|
"STRATEGY": {
|
|
"value": "0"
|
|
}
|
|
}
|
|
},
|
|
"s00_couplers": {
|
|
"interface_ports": {
|
|
"M_AXI": {
|
|
"mode": "Master",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
},
|
|
"S_AXI": {
|
|
"mode": "Slave",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
}
|
|
},
|
|
"ports": {
|
|
"M_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "M_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "M_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"M_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
},
|
|
"S_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "S_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "S_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"S_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
}
|
|
},
|
|
"components": {
|
|
"auto_pc": {
|
|
"vlnv": "xilinx.com:ip:axi_protocol_converter:2.1",
|
|
"xci_name": "zynq_default_auto_pc_3",
|
|
"parameters": {
|
|
"MI_PROTOCOL": {
|
|
"value": "AXI4"
|
|
},
|
|
"SI_PROTOCOL": {
|
|
"value": "AXI3"
|
|
}
|
|
}
|
|
},
|
|
"auto_us": {
|
|
"vlnv": "xilinx.com:ip:axi_dwidth_converter:2.1",
|
|
"xci_name": "zynq_default_auto_us_0",
|
|
"parameters": {
|
|
"MI_DATA_WIDTH": {
|
|
"value": "128"
|
|
},
|
|
"SI_DATA_WIDTH": {
|
|
"value": "32"
|
|
}
|
|
}
|
|
}
|
|
},
|
|
"interface_nets": {
|
|
"auto_pc_to_auto_us": {
|
|
"interface_ports": [
|
|
"auto_pc/M_AXI",
|
|
"auto_us/S_AXI"
|
|
]
|
|
},
|
|
"auto_us_to_s00_couplers": {
|
|
"interface_ports": [
|
|
"M_AXI",
|
|
"auto_us/M_AXI"
|
|
]
|
|
},
|
|
"s00_couplers_to_auto_pc": {
|
|
"interface_ports": [
|
|
"S_AXI",
|
|
"auto_pc/S_AXI"
|
|
]
|
|
}
|
|
},
|
|
"nets": {
|
|
"S_ACLK_1": {
|
|
"ports": [
|
|
"S_ACLK",
|
|
"auto_pc/aclk",
|
|
"auto_us/s_axi_aclk"
|
|
]
|
|
},
|
|
"S_ARESETN_1": {
|
|
"ports": [
|
|
"S_ARESETN",
|
|
"auto_pc/aresetn",
|
|
"auto_us/s_axi_aresetn"
|
|
]
|
|
}
|
|
}
|
|
},
|
|
"s01_couplers": {
|
|
"interface_ports": {
|
|
"M_AXI": {
|
|
"mode": "Master",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
},
|
|
"S_AXI": {
|
|
"mode": "Slave",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
}
|
|
},
|
|
"ports": {
|
|
"M_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "M_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "M_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"M_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
},
|
|
"S_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "S_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "S_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"S_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
}
|
|
},
|
|
"interface_nets": {
|
|
"s01_couplers_to_s01_couplers": {
|
|
"interface_ports": [
|
|
"S_AXI",
|
|
"M_AXI"
|
|
]
|
|
}
|
|
}
|
|
},
|
|
"m00_couplers": {
|
|
"interface_ports": {
|
|
"M_AXI": {
|
|
"mode": "Master",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
},
|
|
"S_AXI": {
|
|
"mode": "Slave",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
}
|
|
},
|
|
"ports": {
|
|
"M_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "M_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "M_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"M_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
},
|
|
"S_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "S_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "S_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"S_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
}
|
|
},
|
|
"interface_nets": {
|
|
"m00_couplers_to_m00_couplers": {
|
|
"interface_ports": [
|
|
"S_AXI",
|
|
"M_AXI"
|
|
]
|
|
}
|
|
}
|
|
},
|
|
"m01_couplers": {
|
|
"interface_ports": {
|
|
"M_AXI": {
|
|
"mode": "Master",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
},
|
|
"S_AXI": {
|
|
"mode": "Slave",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
}
|
|
},
|
|
"ports": {
|
|
"M_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "M_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "M_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"M_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
},
|
|
"S_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "S_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "S_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"S_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
}
|
|
},
|
|
"components": {
|
|
"auto_cc": {
|
|
"vlnv": "xilinx.com:ip:axi_clock_converter:2.1",
|
|
"xci_name": "zynq_default_auto_cc_0"
|
|
},
|
|
"auto_ds": {
|
|
"vlnv": "xilinx.com:ip:axi_dwidth_converter:2.1",
|
|
"xci_name": "zynq_default_auto_ds_1",
|
|
"parameters": {
|
|
"MI_DATA_WIDTH": {
|
|
"value": "32"
|
|
},
|
|
"SI_DATA_WIDTH": {
|
|
"value": "128"
|
|
}
|
|
}
|
|
},
|
|
"auto_pc": {
|
|
"vlnv": "xilinx.com:ip:axi_protocol_converter:2.1",
|
|
"xci_name": "zynq_default_auto_pc_1",
|
|
"parameters": {
|
|
"MI_PROTOCOL": {
|
|
"value": "AXI4LITE"
|
|
},
|
|
"SI_PROTOCOL": {
|
|
"value": "AXI4"
|
|
}
|
|
}
|
|
}
|
|
},
|
|
"interface_nets": {
|
|
"m01_couplers_to_auto_cc": {
|
|
"interface_ports": [
|
|
"S_AXI",
|
|
"auto_cc/S_AXI"
|
|
]
|
|
},
|
|
"auto_cc_to_auto_ds": {
|
|
"interface_ports": [
|
|
"auto_cc/M_AXI",
|
|
"auto_ds/S_AXI"
|
|
]
|
|
},
|
|
"auto_pc_to_m01_couplers": {
|
|
"interface_ports": [
|
|
"M_AXI",
|
|
"auto_pc/M_AXI"
|
|
]
|
|
},
|
|
"auto_ds_to_auto_pc": {
|
|
"interface_ports": [
|
|
"auto_ds/M_AXI",
|
|
"auto_pc/S_AXI"
|
|
]
|
|
}
|
|
},
|
|
"nets": {
|
|
"M_ACLK_1": {
|
|
"ports": [
|
|
"M_ACLK",
|
|
"auto_cc/m_axi_aclk",
|
|
"auto_ds/s_axi_aclk",
|
|
"auto_pc/aclk"
|
|
]
|
|
},
|
|
"S_ACLK_1": {
|
|
"ports": [
|
|
"S_ACLK",
|
|
"auto_cc/s_axi_aclk"
|
|
]
|
|
},
|
|
"M_ARESETN_1": {
|
|
"ports": [
|
|
"M_ARESETN",
|
|
"auto_cc/m_axi_aresetn",
|
|
"auto_ds/s_axi_aresetn",
|
|
"auto_pc/aresetn"
|
|
]
|
|
},
|
|
"S_ARESETN_1": {
|
|
"ports": [
|
|
"S_ARESETN",
|
|
"auto_cc/s_axi_aresetn"
|
|
]
|
|
}
|
|
}
|
|
},
|
|
"m02_couplers": {
|
|
"interface_ports": {
|
|
"M_AXI": {
|
|
"mode": "Master",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
},
|
|
"S_AXI": {
|
|
"mode": "Slave",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
}
|
|
},
|
|
"ports": {
|
|
"M_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "M_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "M_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"M_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
},
|
|
"S_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "S_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "S_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"S_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
}
|
|
},
|
|
"components": {
|
|
"auto_ds": {
|
|
"vlnv": "xilinx.com:ip:axi_dwidth_converter:2.1",
|
|
"xci_name": "zynq_default_auto_ds_2",
|
|
"parameters": {
|
|
"MI_DATA_WIDTH": {
|
|
"value": "32"
|
|
},
|
|
"SI_DATA_WIDTH": {
|
|
"value": "128"
|
|
}
|
|
}
|
|
},
|
|
"auto_pc": {
|
|
"vlnv": "xilinx.com:ip:axi_protocol_converter:2.1",
|
|
"xci_name": "zynq_default_auto_pc_2",
|
|
"parameters": {
|
|
"MI_PROTOCOL": {
|
|
"value": "AXI4LITE"
|
|
},
|
|
"SI_PROTOCOL": {
|
|
"value": "AXI4"
|
|
}
|
|
}
|
|
}
|
|
},
|
|
"interface_nets": {
|
|
"m02_couplers_to_auto_ds": {
|
|
"interface_ports": [
|
|
"S_AXI",
|
|
"auto_ds/S_AXI"
|
|
]
|
|
},
|
|
"auto_ds_to_auto_pc": {
|
|
"interface_ports": [
|
|
"auto_ds/M_AXI",
|
|
"auto_pc/S_AXI"
|
|
]
|
|
},
|
|
"auto_pc_to_m02_couplers": {
|
|
"interface_ports": [
|
|
"M_AXI",
|
|
"auto_pc/M_AXI"
|
|
]
|
|
}
|
|
},
|
|
"nets": {
|
|
"S_ACLK_1": {
|
|
"ports": [
|
|
"S_ACLK",
|
|
"auto_ds/s_axi_aclk",
|
|
"auto_pc/aclk"
|
|
]
|
|
},
|
|
"S_ARESETN_1": {
|
|
"ports": [
|
|
"S_ARESETN",
|
|
"auto_ds/s_axi_aresetn",
|
|
"auto_pc/aresetn"
|
|
]
|
|
}
|
|
}
|
|
}
|
|
},
|
|
"interface_nets": {
|
|
"s01_couplers_to_xbar": {
|
|
"interface_ports": [
|
|
"s01_couplers/M_AXI",
|
|
"xbar/S01_AXI"
|
|
]
|
|
},
|
|
"m00_couplers_to_axi_interconnect_1": {
|
|
"interface_ports": [
|
|
"M00_AXI",
|
|
"m00_couplers/M_AXI"
|
|
]
|
|
},
|
|
"s00_couplers_to_xbar": {
|
|
"interface_ports": [
|
|
"s00_couplers/M_AXI",
|
|
"xbar/S00_AXI"
|
|
]
|
|
},
|
|
"axi_interconnect_1_to_s01_couplers": {
|
|
"interface_ports": [
|
|
"S01_AXI",
|
|
"s01_couplers/S_AXI"
|
|
]
|
|
},
|
|
"axi_interconnect_1_to_s00_couplers": {
|
|
"interface_ports": [
|
|
"S00_AXI",
|
|
"s00_couplers/S_AXI"
|
|
]
|
|
},
|
|
"xbar_to_m00_couplers": {
|
|
"interface_ports": [
|
|
"xbar/M00_AXI",
|
|
"m00_couplers/S_AXI"
|
|
]
|
|
},
|
|
"m01_couplers_to_axi_interconnect_1": {
|
|
"interface_ports": [
|
|
"M01_AXI",
|
|
"m01_couplers/M_AXI"
|
|
]
|
|
},
|
|
"m02_couplers_to_axi_interconnect_1": {
|
|
"interface_ports": [
|
|
"M02_AXI",
|
|
"m02_couplers/M_AXI"
|
|
]
|
|
},
|
|
"xbar_to_m01_couplers": {
|
|
"interface_ports": [
|
|
"xbar/M01_AXI",
|
|
"m01_couplers/S_AXI"
|
|
]
|
|
},
|
|
"xbar_to_m02_couplers": {
|
|
"interface_ports": [
|
|
"xbar/M02_AXI",
|
|
"m02_couplers/S_AXI"
|
|
]
|
|
}
|
|
},
|
|
"nets": {
|
|
"axi_interconnect_1_ACLK_net": {
|
|
"ports": [
|
|
"ACLK",
|
|
"xbar/aclk",
|
|
"s00_couplers/M_ACLK",
|
|
"s01_couplers/M_ACLK",
|
|
"m00_couplers/S_ACLK",
|
|
"m01_couplers/S_ACLK",
|
|
"m02_couplers/S_ACLK"
|
|
]
|
|
},
|
|
"axi_interconnect_1_ARESETN_net": {
|
|
"ports": [
|
|
"ARESETN",
|
|
"xbar/aresetn",
|
|
"s00_couplers/M_ARESETN",
|
|
"s01_couplers/M_ARESETN",
|
|
"m00_couplers/S_ARESETN",
|
|
"m01_couplers/S_ARESETN",
|
|
"m02_couplers/S_ARESETN"
|
|
]
|
|
},
|
|
"S00_ACLK_1": {
|
|
"ports": [
|
|
"S00_ACLK",
|
|
"s00_couplers/S_ACLK"
|
|
]
|
|
},
|
|
"S00_ARESETN_1": {
|
|
"ports": [
|
|
"S00_ARESETN",
|
|
"s00_couplers/S_ARESETN"
|
|
]
|
|
},
|
|
"S01_ACLK_1": {
|
|
"ports": [
|
|
"S01_ACLK",
|
|
"s01_couplers/S_ACLK"
|
|
]
|
|
},
|
|
"S01_ARESETN_1": {
|
|
"ports": [
|
|
"S01_ARESETN",
|
|
"s01_couplers/S_ARESETN"
|
|
]
|
|
},
|
|
"M00_ACLK_1": {
|
|
"ports": [
|
|
"M00_ACLK",
|
|
"m00_couplers/M_ACLK"
|
|
]
|
|
},
|
|
"M00_ARESETN_1": {
|
|
"ports": [
|
|
"M00_ARESETN",
|
|
"m00_couplers/M_ARESETN"
|
|
]
|
|
},
|
|
"M01_ACLK_1": {
|
|
"ports": [
|
|
"M01_ACLK",
|
|
"m01_couplers/M_ACLK"
|
|
]
|
|
},
|
|
"M01_ARESETN_1": {
|
|
"ports": [
|
|
"M01_ARESETN",
|
|
"m01_couplers/M_ARESETN"
|
|
]
|
|
},
|
|
"M02_ACLK_1": {
|
|
"ports": [
|
|
"M02_ACLK",
|
|
"m02_couplers/M_ACLK"
|
|
]
|
|
},
|
|
"M02_ARESETN_1": {
|
|
"ports": [
|
|
"M02_ARESETN",
|
|
"m02_couplers/M_ARESETN"
|
|
]
|
|
}
|
|
}
|
|
},
|
|
"axi_interconnect_2": {
|
|
"vlnv": "xilinx.com:ip:axi_interconnect:2.1",
|
|
"xci_name": "zynq_default_axi_interconnect_1_0",
|
|
"parameters": {
|
|
"NUM_MI": {
|
|
"value": "2"
|
|
},
|
|
"NUM_SI": {
|
|
"value": "1"
|
|
}
|
|
},
|
|
"interface_ports": {
|
|
"S00_AXI": {
|
|
"mode": "Slave",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
},
|
|
"M00_AXI": {
|
|
"mode": "Master",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
},
|
|
"M01_AXI": {
|
|
"mode": "Master",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
}
|
|
},
|
|
"ports": {
|
|
"ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_RESET": {
|
|
"value": "ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
},
|
|
"S00_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "S00_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "S00_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"S00_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
},
|
|
"M00_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "M00_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "M00_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"M00_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
},
|
|
"M01_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "M01_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "M01_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"M01_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
}
|
|
},
|
|
"components": {
|
|
"xbar": {
|
|
"vlnv": "xilinx.com:ip:axi_crossbar:2.1",
|
|
"xci_name": "zynq_default_xbar_2",
|
|
"parameters": {
|
|
"NUM_MI": {
|
|
"value": "2"
|
|
},
|
|
"NUM_SI": {
|
|
"value": "1"
|
|
},
|
|
"STRATEGY": {
|
|
"value": "0"
|
|
}
|
|
}
|
|
},
|
|
"s00_couplers": {
|
|
"interface_ports": {
|
|
"M_AXI": {
|
|
"mode": "Master",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
},
|
|
"S_AXI": {
|
|
"mode": "Slave",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
}
|
|
},
|
|
"ports": {
|
|
"M_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "M_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "M_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"M_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
},
|
|
"S_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "S_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "S_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"S_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
}
|
|
},
|
|
"interface_nets": {
|
|
"s00_couplers_to_s00_couplers": {
|
|
"interface_ports": [
|
|
"S_AXI",
|
|
"M_AXI"
|
|
]
|
|
}
|
|
}
|
|
},
|
|
"m00_couplers": {
|
|
"interface_ports": {
|
|
"M_AXI": {
|
|
"mode": "Master",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
},
|
|
"S_AXI": {
|
|
"mode": "Slave",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
}
|
|
},
|
|
"ports": {
|
|
"M_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "M_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "M_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"M_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
},
|
|
"S_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "S_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "S_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"S_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
}
|
|
},
|
|
"interface_nets": {
|
|
"m00_couplers_to_m00_couplers": {
|
|
"interface_ports": [
|
|
"S_AXI",
|
|
"M_AXI"
|
|
]
|
|
}
|
|
}
|
|
},
|
|
"m01_couplers": {
|
|
"interface_ports": {
|
|
"M_AXI": {
|
|
"mode": "Master",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
},
|
|
"S_AXI": {
|
|
"mode": "Slave",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
}
|
|
},
|
|
"ports": {
|
|
"M_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "M_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "M_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"M_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
},
|
|
"S_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "S_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "S_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"S_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
}
|
|
},
|
|
"interface_nets": {
|
|
"m01_couplers_to_m01_couplers": {
|
|
"interface_ports": [
|
|
"S_AXI",
|
|
"M_AXI"
|
|
]
|
|
}
|
|
}
|
|
}
|
|
},
|
|
"interface_nets": {
|
|
"xbar_to_m01_couplers": {
|
|
"interface_ports": [
|
|
"xbar/M01_AXI",
|
|
"m01_couplers/S_AXI"
|
|
]
|
|
},
|
|
"axi_interconnect_2_to_s00_couplers": {
|
|
"interface_ports": [
|
|
"S00_AXI",
|
|
"s00_couplers/S_AXI"
|
|
]
|
|
},
|
|
"s00_couplers_to_xbar": {
|
|
"interface_ports": [
|
|
"s00_couplers/M_AXI",
|
|
"xbar/S00_AXI"
|
|
]
|
|
},
|
|
"m00_couplers_to_axi_interconnect_2": {
|
|
"interface_ports": [
|
|
"M00_AXI",
|
|
"m00_couplers/M_AXI"
|
|
]
|
|
},
|
|
"xbar_to_m00_couplers": {
|
|
"interface_ports": [
|
|
"xbar/M00_AXI",
|
|
"m00_couplers/S_AXI"
|
|
]
|
|
},
|
|
"m01_couplers_to_axi_interconnect_2": {
|
|
"interface_ports": [
|
|
"M01_AXI",
|
|
"m01_couplers/M_AXI"
|
|
]
|
|
}
|
|
},
|
|
"nets": {
|
|
"axi_interconnect_2_ACLK_net": {
|
|
"ports": [
|
|
"ACLK",
|
|
"xbar/aclk",
|
|
"s00_couplers/M_ACLK",
|
|
"m00_couplers/S_ACLK",
|
|
"m01_couplers/S_ACLK"
|
|
]
|
|
},
|
|
"axi_interconnect_2_ARESETN_net": {
|
|
"ports": [
|
|
"ARESETN",
|
|
"xbar/aresetn",
|
|
"s00_couplers/M_ARESETN",
|
|
"m00_couplers/S_ARESETN",
|
|
"m01_couplers/S_ARESETN"
|
|
]
|
|
},
|
|
"S00_ACLK_1": {
|
|
"ports": [
|
|
"S00_ACLK",
|
|
"s00_couplers/S_ACLK"
|
|
]
|
|
},
|
|
"S00_ARESETN_1": {
|
|
"ports": [
|
|
"S00_ARESETN",
|
|
"s00_couplers/S_ARESETN"
|
|
]
|
|
},
|
|
"M00_ACLK_1": {
|
|
"ports": [
|
|
"M00_ACLK",
|
|
"m00_couplers/M_ACLK"
|
|
]
|
|
},
|
|
"M00_ARESETN_1": {
|
|
"ports": [
|
|
"M00_ARESETN",
|
|
"m00_couplers/M_ARESETN"
|
|
]
|
|
},
|
|
"M01_ACLK_1": {
|
|
"ports": [
|
|
"M01_ACLK",
|
|
"m01_couplers/M_ACLK"
|
|
]
|
|
},
|
|
"M01_ARESETN_1": {
|
|
"ports": [
|
|
"M01_ARESETN",
|
|
"m01_couplers/M_ARESETN"
|
|
]
|
|
}
|
|
}
|
|
}
|
|
},
|
|
"interface_nets": {
|
|
"axi_pcie_0_M_AXI": {
|
|
"interface_ports": [
|
|
"axi_pcie_0/M_AXI",
|
|
"axi_interconnect_0/S00_AXI"
|
|
]
|
|
},
|
|
"axi_interconnect_0_M00_AXI": {
|
|
"interface_ports": [
|
|
"axi_interconnect_0/M00_AXI",
|
|
"processing_system7_0/S_AXI_HP0"
|
|
]
|
|
},
|
|
"axi_interconnect_1_M02_AXI": {
|
|
"interface_ports": [
|
|
"axi_interconnect_1/M02_AXI",
|
|
"axi_cdma_0/S_AXI_LITE"
|
|
]
|
|
},
|
|
"axi_interconnect_2_M01_AXI": {
|
|
"interface_ports": [
|
|
"axi_interconnect_2/M01_AXI",
|
|
"axi_interconnect_1/S01_AXI"
|
|
]
|
|
},
|
|
"axi_interconnect_2_M00_AXI": {
|
|
"interface_ports": [
|
|
"axi_interconnect_2/M00_AXI",
|
|
"axi_interconnect_0/S01_AXI"
|
|
]
|
|
},
|
|
"processing_system7_0_FIXED_IO": {
|
|
"interface_ports": [
|
|
"FIXED_IO",
|
|
"processing_system7_0/FIXED_IO"
|
|
]
|
|
},
|
|
"processing_system7_0_M_AXI_GP0": {
|
|
"interface_ports": [
|
|
"processing_system7_0/M_AXI_GP0",
|
|
"axi_interconnect_1/S00_AXI"
|
|
]
|
|
},
|
|
"axi_interconnect_1_M00_AXI": {
|
|
"interface_ports": [
|
|
"axi_interconnect_1/M00_AXI",
|
|
"axi_pcie_0/S_AXI"
|
|
]
|
|
},
|
|
"processing_system7_0_DDR": {
|
|
"interface_ports": [
|
|
"DDR",
|
|
"processing_system7_0/DDR"
|
|
]
|
|
},
|
|
"axi_cdma_0_M_AXI": {
|
|
"interface_ports": [
|
|
"axi_cdma_0/M_AXI",
|
|
"axi_interconnect_2/S00_AXI"
|
|
]
|
|
},
|
|
"axi_pcie_0_pcie_7x_mgt": {
|
|
"interface_ports": [
|
|
"pcie_7x_mgt",
|
|
"axi_pcie_0/pcie_7x_mgt"
|
|
]
|
|
},
|
|
"axi_interconnect_1_M01_AXI": {
|
|
"interface_ports": [
|
|
"axi_interconnect_1/M01_AXI",
|
|
"axi_pcie_0/S_AXI_CTL"
|
|
]
|
|
}
|
|
},
|
|
"nets": {
|
|
"xlconstant_0_dout": {
|
|
"ports": [
|
|
"xlconstant_0/dout",
|
|
"axi_pcie_0/INTX_MSI_Request"
|
|
]
|
|
},
|
|
"axi_pcie_0_axi_ctl_aclk_out": {
|
|
"ports": [
|
|
"axi_pcie_0/axi_ctl_aclk_out",
|
|
"proc_sys_reset_0/slowest_sync_clk",
|
|
"axi_interconnect_1/M01_ACLK"
|
|
]
|
|
},
|
|
"axi_pcie_0_mmcm_lock": {
|
|
"ports": [
|
|
"axi_pcie_0/mmcm_lock",
|
|
"proc_sys_reset_0/dcm_locked",
|
|
"proc_sys_reset_1/dcm_locked"
|
|
]
|
|
},
|
|
"processing_system7_0_FCLK_RESET0_N": {
|
|
"ports": [
|
|
"processing_system7_0/FCLK_RESET0_N",
|
|
"proc_sys_reset_0/ext_reset_in",
|
|
"proc_sys_reset_1/ext_reset_in"
|
|
]
|
|
},
|
|
"proc_sys_reset_0_peripheral_reset": {
|
|
"ports": [
|
|
"proc_sys_reset_0/peripheral_reset",
|
|
"perst"
|
|
]
|
|
},
|
|
"proc_sys_reset_0_peripheral_aresetn": {
|
|
"ports": [
|
|
"proc_sys_reset_0/peripheral_aresetn",
|
|
"axi_pcie_0/axi_aresetn",
|
|
"axi_interconnect_1/M01_ARESETN"
|
|
]
|
|
},
|
|
"axi_pcie_0_axi_aclk_out": {
|
|
"ports": [
|
|
"axi_pcie_0/axi_aclk_out",
|
|
"proc_sys_reset_1/slowest_sync_clk",
|
|
"processing_system7_0/M_AXI_GP0_ACLK",
|
|
"processing_system7_0/S_AXI_HP0_ACLK",
|
|
"axi_cdma_0/m_axi_aclk",
|
|
"axi_cdma_0/s_axi_lite_aclk",
|
|
"axi_interconnect_1/ACLK",
|
|
"axi_interconnect_1/S00_ACLK",
|
|
"axi_interconnect_1/M00_ACLK",
|
|
"axi_interconnect_1/S01_ACLK",
|
|
"axi_interconnect_1/M02_ACLK",
|
|
"axi_interconnect_0/ACLK",
|
|
"axi_interconnect_0/S00_ACLK",
|
|
"axi_interconnect_0/M00_ACLK",
|
|
"axi_interconnect_0/S01_ACLK",
|
|
"axi_interconnect_2/ACLK",
|
|
"axi_interconnect_2/S00_ACLK",
|
|
"axi_interconnect_2/M00_ACLK",
|
|
"axi_interconnect_2/M01_ACLK"
|
|
]
|
|
},
|
|
"xlconcat_0_dout": {
|
|
"ports": [
|
|
"xlconcat_0/dout",
|
|
"processing_system7_0/IRQ_F2P"
|
|
]
|
|
},
|
|
"axi_pcie_0_interrupt_out": {
|
|
"ports": [
|
|
"axi_pcie_0/interrupt_out",
|
|
"xlconcat_0/In0"
|
|
]
|
|
},
|
|
"axi_cdma_0_cdma_introut": {
|
|
"ports": [
|
|
"axi_cdma_0/cdma_introut",
|
|
"xlconcat_0/In1"
|
|
]
|
|
},
|
|
"proc_sys_reset_1_peripheral_aresetn": {
|
|
"ports": [
|
|
"proc_sys_reset_1/peripheral_aresetn",
|
|
"axi_cdma_0/s_axi_lite_aresetn",
|
|
"axi_interconnect_0/S00_ARESETN",
|
|
"axi_interconnect_0/M00_ARESETN",
|
|
"axi_interconnect_0/S01_ARESETN",
|
|
"axi_interconnect_1/S00_ARESETN",
|
|
"axi_interconnect_1/M00_ARESETN",
|
|
"axi_interconnect_1/S01_ARESETN",
|
|
"axi_interconnect_1/M02_ARESETN",
|
|
"axi_interconnect_2/S00_ARESETN",
|
|
"axi_interconnect_2/M00_ARESETN",
|
|
"axi_interconnect_2/M01_ARESETN"
|
|
]
|
|
},
|
|
"proc_sys_reset_1_interconnect_aresetn": {
|
|
"ports": [
|
|
"proc_sys_reset_1/interconnect_aresetn",
|
|
"axi_interconnect_0/ARESETN",
|
|
"axi_interconnect_1/ARESETN",
|
|
"axi_interconnect_2/ARESETN"
|
|
]
|
|
},
|
|
"processing_system7_0_FCLK_CLK0": {
|
|
"ports": [
|
|
"processing_system7_0/FCLK_CLK0",
|
|
"axi_pcie_0/REFCLK"
|
|
]
|
|
}
|
|
},
|
|
"addressing": {
|
|
"/processing_system7_0": {
|
|
"address_spaces": {
|
|
"Data": {
|
|
"range": "4G",
|
|
"width": "32",
|
|
"segments": {
|
|
"SEG_axi_cdma_0_Reg": {
|
|
"address_block": "/axi_cdma_0/S_AXI_LITE/Reg",
|
|
"offset": "0x7E200000",
|
|
"range": "64K"
|
|
},
|
|
"SEG_axi_pcie_0_BAR0": {
|
|
"address_block": "/axi_pcie_0/S_AXI/BAR0",
|
|
"offset": "0x40000000",
|
|
"range": "256M"
|
|
},
|
|
"SEG_axi_pcie_0_CTL0": {
|
|
"address_block": "/axi_pcie_0/S_AXI_CTL/CTL0",
|
|
"offset": "0x50000000",
|
|
"range": "64M"
|
|
}
|
|
}
|
|
}
|
|
}
|
|
},
|
|
"/axi_pcie_0": {
|
|
"address_spaces": {
|
|
"M_AXI": {
|
|
"range": "4G",
|
|
"width": "32",
|
|
"segments": {
|
|
"SEG_processing_system7_0_HP0_DDR_LOWOCM": {
|
|
"address_block": "/processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM",
|
|
"offset": "0x00000000",
|
|
"range": "1G"
|
|
}
|
|
}
|
|
}
|
|
}
|
|
},
|
|
"/axi_cdma_0": {
|
|
"address_spaces": {
|
|
"Data": {
|
|
"range": "4G",
|
|
"width": "32",
|
|
"segments": {
|
|
"SEG_axi_pcie_0_BAR0": {
|
|
"address_block": "/axi_pcie_0/S_AXI/BAR0",
|
|
"offset": "0x40000000",
|
|
"range": "256M"
|
|
},
|
|
"SEG_axi_pcie_0_CTL0": {
|
|
"address_block": "/axi_pcie_0/S_AXI_CTL/CTL0",
|
|
"offset": "0x50000000",
|
|
"range": "64M"
|
|
},
|
|
"SEG_processing_system7_0_HP0_DDR_LOWOCM": {
|
|
"address_block": "/processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM",
|
|
"offset": "0x00000000",
|
|
"range": "1G"
|
|
},
|
|
"SEG_axi_cdma_0_Reg": {
|
|
"address_block": "/axi_cdma_0/S_AXI_LITE/Reg",
|
|
"offset": "0x7E200000",
|
|
"range": "64K",
|
|
"is_excluded": "TRUE"
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
} |