684 lines
14 KiB
JSON
684 lines
14 KiB
JSON
{
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"counter": {
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"prefix": "counter",
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"body": [
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"//define the time counter",
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"parameter SET_TIME = $1'd$4;",
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"reg [${1:32}:0] count$2;",
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"reg ${3:impulse};",
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"always@(posedge clock) begin",
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" if (count$2 == SET_TIME) begin",
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" count$2 <= $1'd0;",
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" $3 <= 1'd1;",
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" end",
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" else begin",
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" count$2 <= count$2 + 1'd1;",
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" $3 <= 1'd0;",
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" end",
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"end"
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]
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},
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"divclk": {
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"prefix": "div",
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"body": [
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"reg [${1:3}:0] count$2;",
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"reg clk_div$2;",
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"always@(posedge ${3:clock}) begin",
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" if (count$2 == ${4:3}) begin",
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" count$2 <= $1'd0;",
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" clk_div$2 <= ~clk_div$2;",
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" end",
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" else begin",
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" count$2 <= count$2 + 1'd1;",
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" end",
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"end"
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]
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},
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"lock": {
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"prefix": "lock",
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"body": [
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"reg gate$2;",
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"reg gate$2_buf;",
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"wire gate$2_pos = gate$2 & ~gate$2_buf;",
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"wire gate$2_neg = ~gate$2 & gate$2_buf;",
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"always@(posedge clock) begin",
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" gate$2 <= ${1:signal};",
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" gate$2_buf <= gate$2;",
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"end"
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]
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},
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"posedge": {
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"prefix": "pos",
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"body": [
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"posedge"
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]
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},
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"negedge": {
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"prefix": "neg",
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"body": [
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"negedge"
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]
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},
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"resetn": {
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"prefix": "resetn",
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"body": [
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"reg rst_n_s1, rst_n_s2;",
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"wire sys_rstn",
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"always @ (posedge clock or negedge rstn) begin",
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" if (rstn) begin",
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" rst_n_s2 <= 1'b0;",
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" rst_n_s1 <= 1'b0;",
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" end",
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" rst_n_s1 <= 1'b1;",
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" rst_n_s2 <= rst_n_s1;",
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" end",
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"end",
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"assign sys_rstn = rst_n_s2;"
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],
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"description" : "Asynchronous sys_rstn synchronous release (intel device)"
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},
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"reset": {
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"prefix": "reset",
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"body": [
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"reg rst_s1, rst_s2;",
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"wire sys_rst",
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"always @ (posedge clock or posedge reset) begin",
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" if (reset) begin",
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" rst_s2 <= 1'b0;",
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" rst_s1 <= 1'b0;",
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" end",
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" rst_s1 <= 1'b1;",
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" rst_s2 <= rst_s1;",
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" end",
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"end",
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"assign sys_rst = rst_s2;"
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],
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"description" : "Asynchronous reset synchronous release (xilinx device)"
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},
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"initial sim": {
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"prefix": "inits",
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"body": [
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"initial begin",
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" \\$dumpfile(\"wave.vcd\");",
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" \\$dumpvars(0, ${1:testbench});",
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" #6000 \\$finish;",
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"end"
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],
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"description": "initial for simulation"
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},
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"initial array": {
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"prefix": "inita",
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"body": [
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"integer ${1:i};",
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"initial begin",
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" for ($1 = 0; $1<${2:range}; $1=$1+1) begin",
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" ${3:data}[$1] = 0;",
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" end",
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"end"
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],
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"description": "initial for a array"
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},
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"debug": {
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"prefix": "debug",
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"body": ["(* mark_debug = \"true\" *)"]
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},
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"time": {
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"prefix": "time",
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"body": ["`timescale 1ns / 1ps"]
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},
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"assign": {
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"prefix": "assign",
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"body": ["assign $1 = $2;"]
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},
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"always_ff block": {
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"prefix": "ff",
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"body": [
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"always_ff @( ${1:clock} ) begin : ${2:blockName}",
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" $0;",
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"end"
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],
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"description": "Insert an always_ff block"
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},
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"always_comb block": {
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"prefix": "comb",
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"body": [
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"always_comb begin : ${1:blockName}",
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" $0;",
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"end"
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],
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"description": "Insert an always_comb block"
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},
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"always": {
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"prefix": "alw",
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"body": [
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"always @(*) begin",
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" $1;",
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"end"
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],
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"description": "always @(*)"
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},
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"alwaysposclk": {
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"prefix": "alclk",
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"body": [
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"always @(posedge clock) begin",
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" $1;",
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"end"
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],
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"description": "always @(posedge clock) directly"
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},
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"alwayssyncrst": {
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"prefix": "alsync",
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"body": [
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"always @(posedge clock) begin",
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" if(reset) begin",
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" $1 <= 0;",
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" end",
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" else begin",
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" $2 <= $3;",
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" end",
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"end"
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],
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"description": "synchronous rst (xilinx device)"
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},
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"alwaysasyncrst": {
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"prefix": "alasync",
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"body": [
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"always @(posedge clock or posedge reset) begin",
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" if(reset) begin",
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" $1 <= 0;",
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" end",
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" else begin",
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" $2 <= $3;",
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" end",
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"end"
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],
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"description": "asynchronous rst (xilinx device)"
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},
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"alwayssyncrstn": {
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"prefix": "alsyncn",
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"body": [
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"always @(posedge clock) begin",
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" if(!rstn) begin",
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" $1 <= 0;",
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" end",
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" else begin",
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" $2 <= $3;",
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" end",
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"end"
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],
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"description": "synchronous rstn (intel device)"
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},
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"alwaysasyncrstn": {
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"prefix": "alasyncn",
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"body": [
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"always @(posedge clock or negedge rstn) begin",
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" if(!rstn) begin",
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" $1 <= 0;",
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" end",
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" else begin",
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" $2 <= $3;",
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" end",
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"end"
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],
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"description": "asynchronous rstn (intel device)"
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},
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"beginend": {
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"prefix": "beginend",
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"body": [
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"begin",
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" $1",
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"end"
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],
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"description": "begin ... end"
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},
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"case": {
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"prefix": "case",
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"body": [
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"case (${1:conditions})",
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" $2: $3",
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"\tdefault: $4",
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"endcase"
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],
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"description": "case () ... endcase"
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},
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"module with parameters": {
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"prefix": "modp",
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"body": [
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"module ${1:name} #(",
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" parameter IWIDTH = ${2:12},",
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" parameter OWIDTH = $2",
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") (",
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" input clock,",
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" input reset,",
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" input [IWIDTH - 1 : 0] ${3:data_i},",
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" output [OWIDTH - 1 : 0] ${4:data_o}",
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");",
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" $5",
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"endmodule //$1\n"
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],
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"description": "Insert a module with parameter"
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},
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"module without parameters": {
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"prefix": "mod",
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"body": [
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"module ${1:moduleName} (",
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" input clock,",
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" input reset,",
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" $2",
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");",
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" $3",
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"endmodule"
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],
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"description": "Insert a module without parameter"
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},
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"simple module": {
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"prefix": "module",
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"body": [
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"module ${1:moduleName}($2);",
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" $3",
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"endmodule //$1\n"
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],
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"description": "Insert a common module"
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},
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"generate_for": {
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"prefix": "genfor",
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"body": [
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"genvar ${1:i};",
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"generate for($1 = 0 ; $1 < $2; $1 = $1 + 1) begin : ${3:U}",
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" $4",
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"end",
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"endgenerate"
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]
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},
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"generate_if": {
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"prefix": "genif",
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"body": [
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"generate if(${1:conditional}) begin : ${2:U}",
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" ${3:}",
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"end",
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"endgenerate"
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]
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},
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"generate_case": {
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"prefix": "gencase",
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"body": [
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"generate",
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"case (${1:NUM})",
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"32'd1 : begin : ${2:case1_name}",
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"$3",
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" end",
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"32'd2 : begin : ${4:case1_name}",
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"$5",
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" end",
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"default : begin : NOP end",
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"endcase",
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"endgenerate"
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]
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},
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"if block": {
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"prefix": "if",
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"body": [
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"if (${1:conditions}) begin",
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" $0",
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"end"
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],
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"description": "Insert a if block"
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},
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"include": {
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"prefix": "include",
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"body": [
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"`include \"$1\""
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],
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"description": "`include \"..\""
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},
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"define": {
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"prefix": "define",
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"body": [
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"`define $1 $2"
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],
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"description": "`define var = val"
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},
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"parameter": {
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"prefix": "param",
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"body": [
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"parameter $1 = $2;"
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],
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"description": "paramter var = val;"
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},
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"localparam": {
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"prefix": "param",
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"body": [
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"localparam $1 = $2;"
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],
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"description": "localparam var = val;"
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},
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"ifelse": {
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"prefix": "ifelse",
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"body": [
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"if (${1:conditions}) begin",
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" $2",
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"end",
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"else begin",
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" $3",
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"end"
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],
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"description": "if (...) begin ... end else begin ... end"
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},
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"else": {
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"prefix": "else",
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"body": [
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"else begin",
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" $1",
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"end"
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],
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"description": "else begin ... end"
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},
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"elseif": {
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"prefix": "elif",
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"body": [
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"else if(${1:conditions}) begin",
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" $2",
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"end"
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],
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"description": "else if(conditions) begin ... end"
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},
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"for loop": {
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"prefix": "for",
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"body": [
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"for ($1 = $2; $3; $4) begin",
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" $0",
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"end"
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],
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"description": "for (...) begin ... end"
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},
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"while loop": {
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"prefix": "while",
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"body": [
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"while ($1) begin",
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" $2",
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"end"
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],
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"description": "while (...) begin ... end"
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},
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"function": {
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"prefix": "function",
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"body": [
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"function $1;",
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" $2;",
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" $3",
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"endfunction"
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],
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"description": "function (...) ... endfunction"
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},
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"bit":{
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"prefix":"bit",
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"body":"bit"
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},
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"int":{
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"prefix":"int",
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"body":"int"
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},
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"byte":{
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"prefix":"byte",
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"body":"byte"
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},
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"logic":{
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"prefix":"logic",
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"body":"logic"
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},
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"reg": {
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"prefix": "reg",
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"body": [
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"reg $1;"
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],
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"description": "reg reg_name;"
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},
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"regarray": {
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"prefix": "rega",
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"body": [
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"reg [$1:$2] $3;"
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],
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"description": "reg [N:0] reg_name;"
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},
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"regmemory": {
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"prefix": "regm",
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"body": [
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"reg [$1:$2] $3 [$4:$5];"
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],
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"description": "reg [N:0] reg_name [0:M];"
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},
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"wire": {
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"prefix": "wire",
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"body": [
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"wire $1;"
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],
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"description": "wire wire_name;"
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},
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"wirearray": {
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"prefix": "wirea",
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"body": [
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"wire [$1:$2] $3;"
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],
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"description": "wire [N:0] wire_name;"
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},
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"packed":{
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"prefix":"packed",
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"body":"packed"
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},
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"this":{
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"prefix": "this",
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"body": "this"
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},
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"array":{
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"prefix":"array",
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"body":"[${1:8}:${2:0}]$0",
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"description":"insert [x:y]"
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},
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|
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"typedef struct packed":{
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"prefix":"typedefstructpacked",
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"body":[
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"typedef struct packed {",
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" $0",
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"} ${1:struct_name};"
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],
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"description":"typedef struct packed { ... } name"
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},
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"class":{
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"prefix":"class",
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"body":[
|
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"class ${1:className};",
|
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"\tfunction new();",
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" $0",
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"\tendfunction //new()",
|
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"endclass //${1}"
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],
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"description":"class name; ... endclass"
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},
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"class extends":{
|
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"prefix":"classextends",
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"body":[
|
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"class ${1:className} extends ${2:superClass};",
|
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"\tfunction new();",
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" $0",
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"\tendfunction //new()",
|
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"endclass //${1} extends ${2}"
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],
|
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"description":"class name extends super; ... endclass"
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},
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"task":{
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"prefix":"task",
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"body":[
|
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"task ${1:automatic} ${2:taskName}(${3:arguments});",
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" $0",
|
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"endtask //${1}"
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],
|
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"description":"task name; ... endtask"
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},
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"interface":{
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"prefix":"interface",
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"body":[
|
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"interface ${1:interfacename};",
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" $0",
|
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"endinterface //${1}"
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],
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"description":"interface name; ... endinterface"
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},
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|
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"set Module":{
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"prefix":"setmodule",
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"body":[
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"${1:mod_name} ${2:instance_name} (${3:.*}$0);"
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],
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"description":"set module, mod i0 (.*);"
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},
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|
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"typedef enum":{
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"prefix":"typedefenum",
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"body":[
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"typedef enum ${1:data_type} { $0 } ${2:name};"
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],
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"description":"typedef enum (data_type) { ... } name"
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},
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"enum":{
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"prefix":"enum",
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"body":[
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"enum ${1:data_type} { $0 } ${2:name}"
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],
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"description":"enum (data_type) { ... } name"
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},
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"queue":{
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"prefix":"queue",
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"body":"${1:data_type} ${2:queue_name}[$];",
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"description":"insert queue."
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},
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"mailbox":{
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"prefix":"mailbox",
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"body":[
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"mailbox mbx",
|
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"${1:mbx = new();}"
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],
|
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"description":"insert mailbox instance"
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},
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"Associative array":{
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"prefix":"AA",
|
|
"body":"${1:data_type} ${2:name}[${3:index_type}];$0",
|
|
"description":"insert Associative array(AA)."
|
|
},
|
|
|
|
"assert":{
|
|
"prefix": "assert",
|
|
"body": [
|
|
"assert (${1:condition}) ${2}",
|
|
"else ${3:error_process}"
|
|
],
|
|
"description": "insert assert() ... else ..."
|
|
},
|
|
|
|
"fork-join":{
|
|
"prefix": "forkjoin",
|
|
"body": [
|
|
"fork",
|
|
" $0",
|
|
"join"
|
|
],
|
|
"description": "fork ... join"
|
|
},
|
|
|
|
"forever":{
|
|
"prefix": "forever",
|
|
"body": [
|
|
"forever begin",
|
|
" $0",
|
|
"end"
|
|
],
|
|
"description": "forever begin ... end"
|
|
},
|
|
|
|
"signed":{
|
|
"prefix": "$signed",
|
|
"body": [
|
|
"\\$signed($1)"
|
|
],
|
|
"description": ""
|
|
},
|
|
|
|
"unsigned":{
|
|
"prefix": "$unsigned",
|
|
"body": [
|
|
"\\$unsigned($1)"
|
|
],
|
|
"description": ""
|
|
},
|
|
|
|
"wavedrom comment": {
|
|
"prefix" : "wavedrom",
|
|
"body": [
|
|
"/* @wavedrom",
|
|
"{",
|
|
" $1",
|
|
"}",
|
|
"*/"
|
|
]
|
|
}
|
|
} |