519 lines
14 KiB
Plaintext
519 lines
14 KiB
Plaintext
{
|
|
"design": {
|
|
"design_info": {
|
|
"boundary_crc": "0xA1D73E4ECA8CEDF5",
|
|
"name": "MicroBlaze_default",
|
|
"synth_flow_mode": "Hierarchical",
|
|
"validated": "true"
|
|
},
|
|
"design_tree": {
|
|
"microblaze_0": "",
|
|
"microblaze_0_local_memory": {
|
|
"dlmb_v10": "",
|
|
"ilmb_v10": "",
|
|
"dlmb_bram_if_cntlr": "",
|
|
"ilmb_bram_if_cntlr": "",
|
|
"lmb_bram": ""
|
|
},
|
|
"mdm_1": "",
|
|
"rst_clk_wiz_1_100M": "",
|
|
"axi_gpio_0": "",
|
|
"microblaze_0_axi_periph": {
|
|
"s00_couplers": {}
|
|
}
|
|
},
|
|
"interface_ports": {
|
|
"gpio_rtl_0": {
|
|
"mode": "Master",
|
|
"vlnv": "xilinx.com:interface:gpio_rtl:1.0"
|
|
}
|
|
},
|
|
"ports": {
|
|
"cpu_clk": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_RESET": {
|
|
"value": "cpu_rst_n"
|
|
},
|
|
"CLK_DOMAIN": {
|
|
"value": "MicroBlaze_default_Clk_0",
|
|
"value_src": "default"
|
|
},
|
|
"FREQ_HZ": {
|
|
"value": "100000000",
|
|
"value_src": "default"
|
|
},
|
|
"INSERT_VIP": {
|
|
"value": "0",
|
|
"value_src": "default"
|
|
},
|
|
"PHASE": {
|
|
"value": "0.000",
|
|
"value_src": "default"
|
|
}
|
|
}
|
|
},
|
|
"cpu_rst_n": {
|
|
"type": "rst",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"INSERT_VIP": {
|
|
"value": "0",
|
|
"value_src": "default"
|
|
},
|
|
"POLARITY": {
|
|
"value": "ACTIVE_LOW"
|
|
}
|
|
}
|
|
}
|
|
},
|
|
"components": {
|
|
"microblaze_0": {
|
|
"vlnv": "xilinx.com:ip:microblaze:11.0",
|
|
"xci_name": "MicroBlaze_default_microblaze_0_0",
|
|
"parameters": {
|
|
"C_DEBUG_ENABLED": {
|
|
"value": "1"
|
|
},
|
|
"C_D_AXI": {
|
|
"value": "1"
|
|
},
|
|
"C_D_LMB": {
|
|
"value": "1"
|
|
},
|
|
"C_I_LMB": {
|
|
"value": "1"
|
|
}
|
|
},
|
|
"hdl_attributes": {
|
|
"BMM_INFO_PROCESSOR": {
|
|
"value": "microblaze-le > MicroBlaze_default microblaze_0_local_memory/dlmb_bram_if_cntlr",
|
|
"value_src": "default"
|
|
},
|
|
"KEEP_HIERARCHY": {
|
|
"value": "yes",
|
|
"value_src": "default"
|
|
}
|
|
}
|
|
},
|
|
"microblaze_0_local_memory": {
|
|
"interface_ports": {
|
|
"DLMB": {
|
|
"mode": "MirroredMaster",
|
|
"vlnv": "xilinx.com:interface:lmb_rtl:1.0"
|
|
},
|
|
"ILMB": {
|
|
"mode": "MirroredMaster",
|
|
"vlnv": "xilinx.com:interface:lmb_rtl:1.0"
|
|
}
|
|
},
|
|
"ports": {
|
|
"LMB_Clk": {
|
|
"type": "clk",
|
|
"direction": "I"
|
|
},
|
|
"SYS_Rst": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
}
|
|
},
|
|
"components": {
|
|
"dlmb_v10": {
|
|
"vlnv": "xilinx.com:ip:lmb_v10:3.0",
|
|
"xci_name": "MicroBlaze_default_dlmb_v10_0"
|
|
},
|
|
"ilmb_v10": {
|
|
"vlnv": "xilinx.com:ip:lmb_v10:3.0",
|
|
"xci_name": "MicroBlaze_default_ilmb_v10_0"
|
|
},
|
|
"dlmb_bram_if_cntlr": {
|
|
"vlnv": "xilinx.com:ip:lmb_bram_if_cntlr:4.0",
|
|
"xci_name": "MicroBlaze_default_dlmb_bram_if_cntlr_0",
|
|
"parameters": {
|
|
"C_ECC": {
|
|
"value": "0"
|
|
}
|
|
},
|
|
"hdl_attributes": {
|
|
"BMM_INFO_ADDRESS_SPACE": {
|
|
"value": "byte 0x00000000 32 > MicroBlaze_default microblaze_0_local_memory/lmb_bram",
|
|
"value_src": "default"
|
|
},
|
|
"KEEP_HIERARCHY": {
|
|
"value": "yes",
|
|
"value_src": "default"
|
|
}
|
|
}
|
|
},
|
|
"ilmb_bram_if_cntlr": {
|
|
"vlnv": "xilinx.com:ip:lmb_bram_if_cntlr:4.0",
|
|
"xci_name": "MicroBlaze_default_ilmb_bram_if_cntlr_0",
|
|
"parameters": {
|
|
"C_ECC": {
|
|
"value": "0"
|
|
}
|
|
}
|
|
},
|
|
"lmb_bram": {
|
|
"vlnv": "xilinx.com:ip:blk_mem_gen:8.4",
|
|
"xci_name": "MicroBlaze_default_lmb_bram_0",
|
|
"parameters": {
|
|
"Memory_Type": {
|
|
"value": "True_Dual_Port_RAM"
|
|
},
|
|
"use_bram_block": {
|
|
"value": "BRAM_Controller"
|
|
}
|
|
}
|
|
}
|
|
},
|
|
"interface_nets": {
|
|
"microblaze_0_ilmb_bus": {
|
|
"interface_ports": [
|
|
"ilmb_v10/LMB_Sl_0",
|
|
"ilmb_bram_if_cntlr/SLMB"
|
|
]
|
|
},
|
|
"microblaze_0_dlmb_bus": {
|
|
"interface_ports": [
|
|
"dlmb_v10/LMB_Sl_0",
|
|
"dlmb_bram_if_cntlr/SLMB"
|
|
]
|
|
},
|
|
"microblaze_0_ilmb_cntlr": {
|
|
"interface_ports": [
|
|
"ilmb_bram_if_cntlr/BRAM_PORT",
|
|
"lmb_bram/BRAM_PORTB"
|
|
]
|
|
},
|
|
"microblaze_0_dlmb_cntlr": {
|
|
"interface_ports": [
|
|
"dlmb_bram_if_cntlr/BRAM_PORT",
|
|
"lmb_bram/BRAM_PORTA"
|
|
]
|
|
},
|
|
"microblaze_0_dlmb": {
|
|
"interface_ports": [
|
|
"DLMB",
|
|
"dlmb_v10/LMB_M"
|
|
]
|
|
},
|
|
"microblaze_0_ilmb": {
|
|
"interface_ports": [
|
|
"ILMB",
|
|
"ilmb_v10/LMB_M"
|
|
]
|
|
}
|
|
},
|
|
"nets": {
|
|
"microblaze_0_Clk": {
|
|
"ports": [
|
|
"LMB_Clk",
|
|
"dlmb_v10/LMB_Clk",
|
|
"dlmb_bram_if_cntlr/LMB_Clk",
|
|
"ilmb_v10/LMB_Clk",
|
|
"ilmb_bram_if_cntlr/LMB_Clk"
|
|
]
|
|
},
|
|
"SYS_Rst_1": {
|
|
"ports": [
|
|
"SYS_Rst",
|
|
"dlmb_v10/SYS_Rst",
|
|
"dlmb_bram_if_cntlr/LMB_Rst",
|
|
"ilmb_v10/SYS_Rst",
|
|
"ilmb_bram_if_cntlr/LMB_Rst"
|
|
]
|
|
}
|
|
}
|
|
},
|
|
"mdm_1": {
|
|
"vlnv": "xilinx.com:ip:mdm:3.2",
|
|
"xci_name": "MicroBlaze_default_mdm_1_0"
|
|
},
|
|
"rst_clk_wiz_1_100M": {
|
|
"vlnv": "xilinx.com:ip:proc_sys_reset:5.0",
|
|
"xci_name": "MicroBlaze_default_rst_clk_wiz_1_100M_0"
|
|
},
|
|
"axi_gpio_0": {
|
|
"vlnv": "xilinx.com:ip:axi_gpio:2.0",
|
|
"xci_name": "MicroBlaze_default_axi_gpio_0_0"
|
|
},
|
|
"microblaze_0_axi_periph": {
|
|
"vlnv": "xilinx.com:ip:axi_interconnect:2.1",
|
|
"xci_name": "MicroBlaze_default_microblaze_0_axi_periph_0",
|
|
"parameters": {
|
|
"NUM_MI": {
|
|
"value": "1"
|
|
}
|
|
},
|
|
"interface_ports": {
|
|
"S00_AXI": {
|
|
"mode": "Slave",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
},
|
|
"M00_AXI": {
|
|
"mode": "Master",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
}
|
|
},
|
|
"ports": {
|
|
"ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_RESET": {
|
|
"value": "ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
},
|
|
"S00_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "S00_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "S00_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"S00_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
},
|
|
"M00_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "M00_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "M00_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"M00_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
}
|
|
},
|
|
"components": {
|
|
"s00_couplers": {
|
|
"interface_ports": {
|
|
"M_AXI": {
|
|
"mode": "Master",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
},
|
|
"S_AXI": {
|
|
"mode": "Slave",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
}
|
|
},
|
|
"ports": {
|
|
"M_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "M_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "M_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"M_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
},
|
|
"S_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "S_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "S_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"S_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
}
|
|
},
|
|
"interface_nets": {
|
|
"s00_couplers_to_s00_couplers": {
|
|
"interface_ports": [
|
|
"S_AXI",
|
|
"M_AXI"
|
|
]
|
|
}
|
|
}
|
|
}
|
|
},
|
|
"interface_nets": {
|
|
"microblaze_0_axi_periph_to_s00_couplers": {
|
|
"interface_ports": [
|
|
"S00_AXI",
|
|
"s00_couplers/S_AXI"
|
|
]
|
|
},
|
|
"s00_couplers_to_microblaze_0_axi_periph": {
|
|
"interface_ports": [
|
|
"M00_AXI",
|
|
"s00_couplers/M_AXI"
|
|
]
|
|
}
|
|
},
|
|
"nets": {
|
|
"microblaze_0_axi_periph_ACLK_net": {
|
|
"ports": [
|
|
"M00_ACLK",
|
|
"s00_couplers/M_ACLK"
|
|
]
|
|
},
|
|
"microblaze_0_axi_periph_ARESETN_net": {
|
|
"ports": [
|
|
"M00_ARESETN",
|
|
"s00_couplers/M_ARESETN"
|
|
]
|
|
},
|
|
"S00_ACLK_1": {
|
|
"ports": [
|
|
"S00_ACLK",
|
|
"s00_couplers/S_ACLK"
|
|
]
|
|
},
|
|
"S00_ARESETN_1": {
|
|
"ports": [
|
|
"S00_ARESETN",
|
|
"s00_couplers/S_ARESETN"
|
|
]
|
|
}
|
|
}
|
|
}
|
|
},
|
|
"interface_nets": {
|
|
"microblaze_0_M_AXI_DP": {
|
|
"interface_ports": [
|
|
"microblaze_0/M_AXI_DP",
|
|
"microblaze_0_axi_periph/S00_AXI"
|
|
]
|
|
},
|
|
"microblaze_0_ilmb_1": {
|
|
"interface_ports": [
|
|
"microblaze_0/ILMB",
|
|
"microblaze_0_local_memory/ILMB"
|
|
]
|
|
},
|
|
"microblaze_0_dlmb_1": {
|
|
"interface_ports": [
|
|
"microblaze_0/DLMB",
|
|
"microblaze_0_local_memory/DLMB"
|
|
]
|
|
},
|
|
"microblaze_0_debug": {
|
|
"interface_ports": [
|
|
"mdm_1/MBDEBUG_0",
|
|
"microblaze_0/DEBUG"
|
|
]
|
|
},
|
|
"microblaze_0_axi_periph_M00_AXI": {
|
|
"interface_ports": [
|
|
"microblaze_0_axi_periph/M00_AXI",
|
|
"axi_gpio_0/S_AXI"
|
|
]
|
|
},
|
|
"axi_gpio_0_GPIO": {
|
|
"interface_ports": [
|
|
"gpio_rtl_0",
|
|
"axi_gpio_0/GPIO"
|
|
]
|
|
}
|
|
},
|
|
"nets": {
|
|
"rst_clk_wiz_1_100M_mb_reset": {
|
|
"ports": [
|
|
"rst_clk_wiz_1_100M/mb_reset",
|
|
"microblaze_0/Reset"
|
|
]
|
|
},
|
|
"rst_clk_wiz_1_100M_bus_struct_reset": {
|
|
"ports": [
|
|
"rst_clk_wiz_1_100M/bus_struct_reset",
|
|
"microblaze_0_local_memory/SYS_Rst"
|
|
]
|
|
},
|
|
"mdm_1_debug_sys_rst": {
|
|
"ports": [
|
|
"mdm_1/Debug_SYS_Rst",
|
|
"rst_clk_wiz_1_100M/mb_debug_sys_rst"
|
|
]
|
|
},
|
|
"cpu_clk": {
|
|
"ports": [
|
|
"cpu_clk",
|
|
"microblaze_0/Clk",
|
|
"rst_clk_wiz_1_100M/slowest_sync_clk",
|
|
"microblaze_0_local_memory/LMB_Clk",
|
|
"microblaze_0_axi_periph/S00_ACLK",
|
|
"axi_gpio_0/s_axi_aclk",
|
|
"microblaze_0_axi_periph/M00_ACLK",
|
|
"microblaze_0_axi_periph/ACLK"
|
|
]
|
|
},
|
|
"cpu_rst_n": {
|
|
"ports": [
|
|
"cpu_rst_n",
|
|
"rst_clk_wiz_1_100M/ext_reset_in",
|
|
"microblaze_0_axi_periph/S00_ARESETN",
|
|
"axi_gpio_0/s_axi_aresetn",
|
|
"microblaze_0_axi_periph/M00_ARESETN",
|
|
"microblaze_0_axi_periph/ARESETN"
|
|
]
|
|
}
|
|
},
|
|
"addressing": {
|
|
"/microblaze_0": {
|
|
"address_spaces": {
|
|
"Data": {
|
|
"range": "4G",
|
|
"width": "32",
|
|
"segments": {
|
|
"SEG_axi_gpio_0_Reg": {
|
|
"address_block": "/axi_gpio_0/S_AXI/Reg",
|
|
"offset": "0x40000000",
|
|
"range": "64K"
|
|
},
|
|
"SEG_dlmb_bram_if_cntlr_Mem": {
|
|
"address_block": "/microblaze_0_local_memory/dlmb_bram_if_cntlr/SLMB/Mem",
|
|
"offset": "0x00000000",
|
|
"range": "16K"
|
|
}
|
|
}
|
|
},
|
|
"Instruction": {
|
|
"range": "4G",
|
|
"width": "32",
|
|
"segments": {
|
|
"SEG_ilmb_bram_if_cntlr_Mem": {
|
|
"address_block": "/microblaze_0_local_memory/ilmb_bram_if_cntlr/SLMB/Mem",
|
|
"offset": "0x00000000",
|
|
"range": "16K"
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
} |