2235 lines
62 KiB
Plaintext
2235 lines
62 KiB
Plaintext
{
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"design": {
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"design_info": {
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"boundary_crc": "0x1CBED0B5287DFD82",
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"name": "m3_xIP_default",
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"synth_flow_mode": "None",
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"validated": "true"
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},
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"design_tree": {
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"axi_bram_ctrl_0": "",
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"axi_interconnect_0": {
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"xbar": "",
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"s00_couplers": {
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"auto_pc": ""
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},
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"m00_couplers": {},
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"m01_couplers": {},
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"m02_couplers": {},
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"m03_couplers": {},
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"m04_couplers": {},
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"m05_couplers": {}
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},
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"axi_uartlite_0": "",
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"blk_mem_gen_0": "",
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"daplink_if_0": {
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"axi_interconnect_0": {
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"xbar": "",
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"s00_couplers": {},
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"m00_couplers": {},
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"m01_couplers": {},
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"m02_couplers": {},
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"m03_couplers": {}
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},
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"axi_single_spi_0": "",
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"axi_quad_spi_0": "",
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"axi_xip_quad_spi_0": "",
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"axi_gpio_0": "",
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"axi_protocol_convert_0": "",
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"DAPLink_to_Arty_shield_0": ""
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},
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"xlconcat_0": "",
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"xlconcat_1": "",
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"xlconstant_1": "",
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"Cortex_M3_0": "",
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"clk_wiz": "",
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"rst_clk_wiz_100M": "",
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"axi_gpio_0": "",
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"axi_gpio_1": "",
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"axi_quad_spi_0": ""
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},
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"interface_ports": {
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"DAPLink": {
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"mode": "Master",
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"vlnv": "xilinx.com:interface:gpio_rtl:1.0"
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},
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"usb_uart": {
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"mode": "Master",
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"vlnv": "xilinx.com:interface:uart_rtl:1.0"
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},
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"key_4bit": {
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"mode": "Master",
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"vlnv": "xilinx.com:interface:gpio_rtl:1.0"
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},
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"LED_4bit": {
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"mode": "Master",
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"vlnv": "xilinx.com:interface:gpio_rtl:1.0"
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},
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"qspi_flash": {
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"mode": "Master",
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"vlnv": "xilinx.com:interface:spi_rtl:1.0"
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}
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},
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"ports": {
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"clk_50MHz": {
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"type": "clk",
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"direction": "I",
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"parameters": {
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"CLK_DOMAIN": {
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"value": "m3_for_xilinx_clk_50MHz",
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"value_src": "default"
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},
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"FREQ_HZ": {
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"value": "50000000"
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},
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"INSERT_VIP": {
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"value": "0",
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"value_src": "default"
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},
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"PHASE": {
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"value": "0.000",
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"value_src": "default"
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}
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}
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},
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"sys_rst_n": {
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"type": "rst",
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"direction": "I",
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"parameters": {
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"INSERT_VIP": {
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"value": "0",
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"value_src": "default"
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},
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"POLARITY": {
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"value": "ACTIVE_LOW"
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}
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}
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}
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},
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"components": {
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"axi_bram_ctrl_0": {
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"vlnv": "xilinx.com:ip:axi_bram_ctrl:4.1",
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"xci_name": "m3_for_xilinx_axi_bram_ctrl_0_0",
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"parameters": {
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"PROTOCOL": {
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"value": "AXI4LITE"
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},
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"SINGLE_PORT_BRAM": {
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"value": "1"
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}
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}
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},
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"axi_interconnect_0": {
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"vlnv": "xilinx.com:ip:axi_interconnect:2.1",
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"xci_name": "m3_for_xilinx_axi_interconnect_0_0",
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"parameters": {
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"ENABLE_ADVANCED_OPTIONS": {
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"value": "1"
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},
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"M00_HAS_DATA_FIFO": {
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"value": "0"
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},
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"M00_HAS_REGSLICE": {
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"value": "0"
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},
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"M00_SECURE": {
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"value": "0"
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},
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"M01_HAS_DATA_FIFO": {
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"value": "0"
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},
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"M01_HAS_REGSLICE": {
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"value": "3"
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},
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"M01_SECURE": {
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"value": "0"
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},
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"M02_HAS_REGSLICE": {
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"value": "3"
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},
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"M02_SECURE": {
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"value": "0"
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},
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"M03_HAS_REGSLICE": {
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"value": "3"
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},
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"M04_HAS_REGSLICE": {
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"value": "3"
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},
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"M05_HAS_REGSLICE": {
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"value": "3"
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},
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"NUM_MI": {
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"value": "6"
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},
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"NUM_SI": {
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"value": "1"
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},
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"S00_HAS_REGSLICE": {
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"value": "3"
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},
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"S01_HAS_DATA_FIFO": {
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"value": "1"
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},
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"S01_HAS_REGSLICE": {
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"value": "3"
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},
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"SYNCHRONIZATION_STAGES": {
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"value": "2"
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}
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},
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"interface_ports": {
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"S00_AXI": {
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"mode": "Slave",
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"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
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},
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"M00_AXI": {
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"mode": "Master",
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"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
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},
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"M01_AXI": {
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"mode": "Master",
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"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
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},
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"M02_AXI": {
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"mode": "Master",
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"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
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},
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"M03_AXI": {
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"mode": "Master",
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"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
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},
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"M04_AXI": {
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"mode": "Master",
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"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
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},
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"M05_AXI": {
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"mode": "Master",
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"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
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}
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},
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"ports": {
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"ACLK": {
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"type": "clk",
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"direction": "I",
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"parameters": {
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"ASSOCIATED_RESET": {
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"value": "ARESETN"
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}
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}
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},
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"ARESETN": {
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"type": "rst",
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"direction": "I"
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},
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"S00_ACLK": {
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"type": "clk",
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"direction": "I",
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"parameters": {
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"ASSOCIATED_BUSIF": {
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"value": "S00_AXI"
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},
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"ASSOCIATED_RESET": {
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"value": "S00_ARESETN"
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}
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}
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},
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"S00_ARESETN": {
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"type": "rst",
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"direction": "I"
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},
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"M00_ACLK": {
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"type": "clk",
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"direction": "I",
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"parameters": {
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"ASSOCIATED_BUSIF": {
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"value": "M00_AXI"
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},
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"ASSOCIATED_RESET": {
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"value": "M00_ARESETN"
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}
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}
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},
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"M00_ARESETN": {
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"type": "rst",
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"direction": "I"
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},
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"M01_ACLK": {
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"type": "clk",
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"direction": "I",
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"parameters": {
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"ASSOCIATED_BUSIF": {
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"value": "M01_AXI"
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},
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"ASSOCIATED_RESET": {
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"value": "M01_ARESETN"
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}
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}
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},
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"M01_ARESETN": {
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"type": "rst",
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"direction": "I"
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},
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"M02_ACLK": {
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"type": "clk",
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"direction": "I",
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"parameters": {
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"ASSOCIATED_BUSIF": {
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"value": "M02_AXI"
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},
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"ASSOCIATED_RESET": {
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"value": "M02_ARESETN"
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}
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}
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},
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"M02_ARESETN": {
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"type": "rst",
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"direction": "I"
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},
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"M03_ACLK": {
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"type": "clk",
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"direction": "I",
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"parameters": {
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"ASSOCIATED_BUSIF": {
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"value": "M03_AXI"
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},
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"ASSOCIATED_RESET": {
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"value": "M03_ARESETN"
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}
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}
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},
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"M03_ARESETN": {
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"type": "rst",
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"direction": "I"
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},
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"M04_ACLK": {
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"type": "clk",
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"direction": "I",
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"parameters": {
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"ASSOCIATED_BUSIF": {
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"value": "M04_AXI"
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},
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"ASSOCIATED_RESET": {
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"value": "M04_ARESETN"
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}
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}
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},
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"M04_ARESETN": {
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"type": "rst",
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"direction": "I"
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},
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"M05_ACLK": {
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"type": "clk",
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"direction": "I",
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"parameters": {
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"ASSOCIATED_BUSIF": {
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"value": "M05_AXI"
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|
},
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"ASSOCIATED_RESET": {
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"value": "M05_ARESETN"
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|
}
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}
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},
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"M05_ARESETN": {
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"type": "rst",
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"direction": "I"
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|
}
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|
},
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|
"components": {
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|
"xbar": {
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|
"vlnv": "xilinx.com:ip:axi_crossbar:2.1",
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|
"xci_name": "m3_for_xilinx_xbar_0",
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|
"parameters": {
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|
"M00_SECURE": {
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|
"value": "0"
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|
},
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|
"M01_SECURE": {
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|
"value": "0"
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|
},
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|
"M02_SECURE": {
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|
"value": "0"
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},
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|
"NUM_MI": {
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|
"value": "6"
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|
},
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|
"NUM_SI": {
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|
"value": "1"
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|
},
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"STRATEGY": {
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"value": "0"
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}
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}
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},
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"s00_couplers": {
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"interface_ports": {
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"M_AXI": {
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"mode": "Master",
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|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
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},
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"S_AXI": {
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"mode": "Slave",
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"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
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}
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},
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"ports": {
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"M_ACLK": {
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"type": "clk",
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"direction": "I",
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"parameters": {
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"ASSOCIATED_BUSIF": {
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"value": "M_AXI"
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},
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"ASSOCIATED_RESET": {
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"value": "M_ARESETN"
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}
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}
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},
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"M_ARESETN": {
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"type": "rst",
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"direction": "I"
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},
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"S_ACLK": {
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"type": "clk",
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"direction": "I",
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"parameters": {
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"ASSOCIATED_BUSIF": {
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"value": "S_AXI"
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},
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"ASSOCIATED_RESET": {
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"value": "S_ARESETN"
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}
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}
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},
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"S_ARESETN": {
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"type": "rst",
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"direction": "I"
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}
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},
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"components": {
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"auto_pc": {
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"vlnv": "xilinx.com:ip:axi_protocol_converter:2.1",
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"xci_name": "m3_for_xilinx_auto_pc_0",
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"parameters": {
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"MI_PROTOCOL": {
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"value": "AXI4LITE"
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},
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|
"SI_PROTOCOL": {
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"value": "AXI3"
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}
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}
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}
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},
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|
"interface_nets": {
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|
"auto_pc_to_s00_couplers": {
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|
"interface_ports": [
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"M_AXI",
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|
"auto_pc/M_AXI"
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|
]
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|
},
|
|
"s00_couplers_to_auto_pc": {
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|
"interface_ports": [
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"S_AXI",
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"auto_pc/S_AXI"
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|
]
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}
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},
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|
"nets": {
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|
"S_ACLK_1": {
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|
"ports": [
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"S_ACLK",
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"auto_pc/aclk"
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]
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},
|
|
"S_ARESETN_1": {
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|
"ports": [
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"S_ARESETN",
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|
"auto_pc/aresetn"
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|
]
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}
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|
}
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|
},
|
|
"m00_couplers": {
|
|
"interface_ports": {
|
|
"M_AXI": {
|
|
"mode": "Master",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
},
|
|
"S_AXI": {
|
|
"mode": "Slave",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
}
|
|
},
|
|
"ports": {
|
|
"M_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "M_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "M_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"M_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
},
|
|
"S_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "S_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "S_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"S_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
}
|
|
},
|
|
"interface_nets": {
|
|
"m00_couplers_to_m00_couplers": {
|
|
"interface_ports": [
|
|
"S_AXI",
|
|
"M_AXI"
|
|
]
|
|
}
|
|
}
|
|
},
|
|
"m01_couplers": {
|
|
"interface_ports": {
|
|
"M_AXI": {
|
|
"mode": "Master",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
},
|
|
"S_AXI": {
|
|
"mode": "Slave",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
}
|
|
},
|
|
"ports": {
|
|
"M_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "M_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "M_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"M_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
},
|
|
"S_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "S_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "S_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"S_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
}
|
|
},
|
|
"interface_nets": {
|
|
"m01_couplers_to_m01_couplers": {
|
|
"interface_ports": [
|
|
"S_AXI",
|
|
"M_AXI"
|
|
]
|
|
}
|
|
}
|
|
},
|
|
"m02_couplers": {
|
|
"interface_ports": {
|
|
"M_AXI": {
|
|
"mode": "Master",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
},
|
|
"S_AXI": {
|
|
"mode": "Slave",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
}
|
|
},
|
|
"ports": {
|
|
"M_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "M_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "M_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"M_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
},
|
|
"S_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "S_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "S_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"S_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
}
|
|
},
|
|
"interface_nets": {
|
|
"m02_couplers_to_m02_couplers": {
|
|
"interface_ports": [
|
|
"S_AXI",
|
|
"M_AXI"
|
|
]
|
|
}
|
|
}
|
|
},
|
|
"m03_couplers": {
|
|
"interface_ports": {
|
|
"M_AXI": {
|
|
"mode": "Master",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
},
|
|
"S_AXI": {
|
|
"mode": "Slave",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
}
|
|
},
|
|
"ports": {
|
|
"M_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "M_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "M_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"M_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
},
|
|
"S_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "S_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "S_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"S_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
}
|
|
},
|
|
"interface_nets": {
|
|
"m03_couplers_to_m03_couplers": {
|
|
"interface_ports": [
|
|
"S_AXI",
|
|
"M_AXI"
|
|
]
|
|
}
|
|
}
|
|
},
|
|
"m04_couplers": {
|
|
"interface_ports": {
|
|
"M_AXI": {
|
|
"mode": "Master",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
},
|
|
"S_AXI": {
|
|
"mode": "Slave",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
}
|
|
},
|
|
"ports": {
|
|
"M_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "M_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "M_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"M_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
},
|
|
"S_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "S_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "S_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"S_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
}
|
|
},
|
|
"interface_nets": {
|
|
"m04_couplers_to_m04_couplers": {
|
|
"interface_ports": [
|
|
"S_AXI",
|
|
"M_AXI"
|
|
]
|
|
}
|
|
}
|
|
},
|
|
"m05_couplers": {
|
|
"interface_ports": {
|
|
"M_AXI": {
|
|
"mode": "Master",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
},
|
|
"S_AXI": {
|
|
"mode": "Slave",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
}
|
|
},
|
|
"ports": {
|
|
"M_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "M_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "M_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"M_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
},
|
|
"S_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "S_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "S_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"S_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
}
|
|
},
|
|
"interface_nets": {
|
|
"m05_couplers_to_m05_couplers": {
|
|
"interface_ports": [
|
|
"S_AXI",
|
|
"M_AXI"
|
|
]
|
|
}
|
|
}
|
|
}
|
|
},
|
|
"interface_nets": {
|
|
"axi_interconnect_0_to_s00_couplers": {
|
|
"interface_ports": [
|
|
"S00_AXI",
|
|
"s00_couplers/S_AXI"
|
|
]
|
|
},
|
|
"m00_couplers_to_axi_interconnect_0": {
|
|
"interface_ports": [
|
|
"M00_AXI",
|
|
"m00_couplers/M_AXI"
|
|
]
|
|
},
|
|
"s00_couplers_to_xbar": {
|
|
"interface_ports": [
|
|
"s00_couplers/M_AXI",
|
|
"xbar/S00_AXI"
|
|
]
|
|
},
|
|
"xbar_to_m00_couplers": {
|
|
"interface_ports": [
|
|
"xbar/M00_AXI",
|
|
"m00_couplers/S_AXI"
|
|
]
|
|
},
|
|
"m01_couplers_to_axi_interconnect_0": {
|
|
"interface_ports": [
|
|
"M01_AXI",
|
|
"m01_couplers/M_AXI"
|
|
]
|
|
},
|
|
"xbar_to_m01_couplers": {
|
|
"interface_ports": [
|
|
"xbar/M01_AXI",
|
|
"m01_couplers/S_AXI"
|
|
]
|
|
},
|
|
"m02_couplers_to_axi_interconnect_0": {
|
|
"interface_ports": [
|
|
"M02_AXI",
|
|
"m02_couplers/M_AXI"
|
|
]
|
|
},
|
|
"xbar_to_m02_couplers": {
|
|
"interface_ports": [
|
|
"xbar/M02_AXI",
|
|
"m02_couplers/S_AXI"
|
|
]
|
|
},
|
|
"m03_couplers_to_axi_interconnect_0": {
|
|
"interface_ports": [
|
|
"M03_AXI",
|
|
"m03_couplers/M_AXI"
|
|
]
|
|
},
|
|
"m04_couplers_to_axi_interconnect_0": {
|
|
"interface_ports": [
|
|
"M04_AXI",
|
|
"m04_couplers/M_AXI"
|
|
]
|
|
},
|
|
"xbar_to_m03_couplers": {
|
|
"interface_ports": [
|
|
"xbar/M03_AXI",
|
|
"m03_couplers/S_AXI"
|
|
]
|
|
},
|
|
"m05_couplers_to_axi_interconnect_0": {
|
|
"interface_ports": [
|
|
"M05_AXI",
|
|
"m05_couplers/M_AXI"
|
|
]
|
|
},
|
|
"xbar_to_m04_couplers": {
|
|
"interface_ports": [
|
|
"xbar/M04_AXI",
|
|
"m04_couplers/S_AXI"
|
|
]
|
|
},
|
|
"xbar_to_m05_couplers": {
|
|
"interface_ports": [
|
|
"xbar/M05_AXI",
|
|
"m05_couplers/S_AXI"
|
|
]
|
|
}
|
|
},
|
|
"nets": {
|
|
"axi_interconnect_0_ACLK_net": {
|
|
"ports": [
|
|
"ACLK",
|
|
"xbar/aclk",
|
|
"s00_couplers/S_ACLK",
|
|
"s00_couplers/M_ACLK",
|
|
"m00_couplers/M_ACLK",
|
|
"m01_couplers/M_ACLK",
|
|
"m02_couplers/M_ACLK",
|
|
"m03_couplers/M_ACLK",
|
|
"m04_couplers/M_ACLK",
|
|
"m05_couplers/M_ACLK",
|
|
"m00_couplers/S_ACLK",
|
|
"m01_couplers/S_ACLK",
|
|
"m02_couplers/S_ACLK",
|
|
"m03_couplers/S_ACLK",
|
|
"m04_couplers/S_ACLK",
|
|
"m05_couplers/S_ACLK"
|
|
]
|
|
},
|
|
"axi_interconnect_0_ARESETN_net": {
|
|
"ports": [
|
|
"ARESETN",
|
|
"xbar/aresetn",
|
|
"s00_couplers/S_ARESETN",
|
|
"s00_couplers/M_ARESETN",
|
|
"m00_couplers/M_ARESETN",
|
|
"m01_couplers/M_ARESETN",
|
|
"m02_couplers/M_ARESETN",
|
|
"m03_couplers/M_ARESETN",
|
|
"m04_couplers/M_ARESETN",
|
|
"m05_couplers/M_ARESETN",
|
|
"m00_couplers/S_ARESETN",
|
|
"m01_couplers/S_ARESETN",
|
|
"m02_couplers/S_ARESETN",
|
|
"m03_couplers/S_ARESETN",
|
|
"m04_couplers/S_ARESETN",
|
|
"m05_couplers/S_ARESETN"
|
|
]
|
|
}
|
|
}
|
|
},
|
|
"axi_uartlite_0": {
|
|
"vlnv": "xilinx.com:ip:axi_uartlite:2.0",
|
|
"xci_name": "m3_for_xilinx_axi_uartlite_0_0",
|
|
"parameters": {
|
|
"C_BAUDRATE": {
|
|
"value": "115200"
|
|
},
|
|
"C_S_AXI_ACLK_FREQ_HZ": {
|
|
"value": "50000000"
|
|
},
|
|
"UARTLITE_BOARD_INTERFACE": {
|
|
"value": "Custom"
|
|
},
|
|
"USE_BOARD_FLOW": {
|
|
"value": "true"
|
|
}
|
|
}
|
|
},
|
|
"blk_mem_gen_0": {
|
|
"vlnv": "xilinx.com:ip:blk_mem_gen:8.4",
|
|
"xci_name": "m3_for_xilinx_blk_mem_gen_0_0",
|
|
"parameters": {
|
|
"EN_SAFETY_CKT": {
|
|
"value": "false"
|
|
}
|
|
}
|
|
},
|
|
"daplink_if_0": {
|
|
"interface_ports": {
|
|
"S_AXI": {
|
|
"mode": "Slave",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
},
|
|
"UART_out": {
|
|
"mode": "Master",
|
|
"vlnv": "xilinx.com:interface:uart_rtl:1.0"
|
|
},
|
|
"Shield_out": {
|
|
"mode": "Master",
|
|
"vlnv": "xilinx.com:interface:gpio_rtl:1.0"
|
|
},
|
|
"C_AXI": {
|
|
"mode": "Slave",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
}
|
|
},
|
|
"ports": {
|
|
"s_axi_aclk": {
|
|
"direction": "I"
|
|
},
|
|
"s_axi_aresetn": {
|
|
"direction": "I"
|
|
},
|
|
"DAPLink_fittedn": {
|
|
"direction": "O"
|
|
},
|
|
"qspi_irq": {
|
|
"direction": "O"
|
|
},
|
|
"ext_spi_clk": {
|
|
"direction": "I"
|
|
},
|
|
"uart_rxd_axi": {
|
|
"direction": "O"
|
|
},
|
|
"SWDI": {
|
|
"direction": "O"
|
|
},
|
|
"SWCLK": {
|
|
"direction": "O"
|
|
},
|
|
"nSRST": {
|
|
"direction": "O"
|
|
},
|
|
"SWDOEN": {
|
|
"direction": "I"
|
|
},
|
|
"SWDO": {
|
|
"direction": "I"
|
|
},
|
|
"uart_txd_axi": {
|
|
"direction": "I"
|
|
},
|
|
"spi_irq": {
|
|
"direction": "O"
|
|
},
|
|
"qspi_xip_irq": {
|
|
"direction": "O"
|
|
}
|
|
},
|
|
"components": {
|
|
"axi_interconnect_0": {
|
|
"vlnv": "xilinx.com:ip:axi_interconnect:2.1",
|
|
"xci_name": "m3_for_xilinx_axi_interconnect_0_1",
|
|
"parameters": {
|
|
"NUM_MI": {
|
|
"value": "4"
|
|
}
|
|
},
|
|
"interface_ports": {
|
|
"S00_AXI": {
|
|
"mode": "Slave",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
},
|
|
"M00_AXI": {
|
|
"mode": "Master",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
},
|
|
"M01_AXI": {
|
|
"mode": "Master",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
},
|
|
"M02_AXI": {
|
|
"mode": "Master",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
},
|
|
"M03_AXI": {
|
|
"mode": "Master",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
}
|
|
},
|
|
"ports": {
|
|
"ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_RESET": {
|
|
"value": "ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
},
|
|
"S00_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "S00_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "S00_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"S00_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
},
|
|
"M00_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "M00_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "M00_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"M00_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
},
|
|
"M01_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "M01_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "M01_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"M01_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
},
|
|
"M02_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "M02_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "M02_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"M02_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
},
|
|
"M03_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "M03_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "M03_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"M03_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
}
|
|
},
|
|
"components": {
|
|
"xbar": {
|
|
"vlnv": "xilinx.com:ip:axi_crossbar:2.1",
|
|
"xci_name": "m3_for_xilinx_xbar_1",
|
|
"parameters": {
|
|
"NUM_MI": {
|
|
"value": "4"
|
|
},
|
|
"NUM_SI": {
|
|
"value": "1"
|
|
},
|
|
"STRATEGY": {
|
|
"value": "0"
|
|
}
|
|
}
|
|
},
|
|
"s00_couplers": {
|
|
"interface_ports": {
|
|
"M_AXI": {
|
|
"mode": "Master",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
},
|
|
"S_AXI": {
|
|
"mode": "Slave",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
}
|
|
},
|
|
"ports": {
|
|
"M_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "M_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "M_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"M_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
},
|
|
"S_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "S_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "S_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"S_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
}
|
|
},
|
|
"interface_nets": {
|
|
"s00_couplers_to_s00_couplers": {
|
|
"interface_ports": [
|
|
"S_AXI",
|
|
"M_AXI"
|
|
]
|
|
}
|
|
}
|
|
},
|
|
"m00_couplers": {
|
|
"interface_ports": {
|
|
"M_AXI": {
|
|
"mode": "Master",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
},
|
|
"S_AXI": {
|
|
"mode": "Slave",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
}
|
|
},
|
|
"ports": {
|
|
"M_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "M_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "M_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"M_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
},
|
|
"S_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "S_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "S_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"S_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
}
|
|
},
|
|
"interface_nets": {
|
|
"m00_couplers_to_m00_couplers": {
|
|
"interface_ports": [
|
|
"S_AXI",
|
|
"M_AXI"
|
|
]
|
|
}
|
|
}
|
|
},
|
|
"m01_couplers": {
|
|
"interface_ports": {
|
|
"M_AXI": {
|
|
"mode": "Master",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
},
|
|
"S_AXI": {
|
|
"mode": "Slave",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
}
|
|
},
|
|
"ports": {
|
|
"M_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "M_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "M_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"M_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
},
|
|
"S_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "S_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "S_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"S_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
}
|
|
},
|
|
"interface_nets": {
|
|
"m01_couplers_to_m01_couplers": {
|
|
"interface_ports": [
|
|
"S_AXI",
|
|
"M_AXI"
|
|
]
|
|
}
|
|
}
|
|
},
|
|
"m02_couplers": {
|
|
"interface_ports": {
|
|
"M_AXI": {
|
|
"mode": "Master",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
},
|
|
"S_AXI": {
|
|
"mode": "Slave",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
}
|
|
},
|
|
"ports": {
|
|
"M_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "M_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "M_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"M_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
},
|
|
"S_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "S_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "S_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"S_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
}
|
|
},
|
|
"interface_nets": {
|
|
"m02_couplers_to_m02_couplers": {
|
|
"interface_ports": [
|
|
"S_AXI",
|
|
"M_AXI"
|
|
]
|
|
}
|
|
}
|
|
},
|
|
"m03_couplers": {
|
|
"interface_ports": {
|
|
"M_AXI": {
|
|
"mode": "Master",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
},
|
|
"S_AXI": {
|
|
"mode": "Slave",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
}
|
|
},
|
|
"ports": {
|
|
"M_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "M_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "M_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"M_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
},
|
|
"S_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "S_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "S_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"S_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
}
|
|
},
|
|
"interface_nets": {
|
|
"m03_couplers_to_m03_couplers": {
|
|
"interface_ports": [
|
|
"S_AXI",
|
|
"M_AXI"
|
|
]
|
|
}
|
|
}
|
|
}
|
|
},
|
|
"interface_nets": {
|
|
"xbar_to_m03_couplers": {
|
|
"interface_ports": [
|
|
"xbar/M03_AXI",
|
|
"m03_couplers/S_AXI"
|
|
]
|
|
},
|
|
"axi_interconnect_0_to_s00_couplers": {
|
|
"interface_ports": [
|
|
"S00_AXI",
|
|
"s00_couplers/S_AXI"
|
|
]
|
|
},
|
|
"s00_couplers_to_xbar": {
|
|
"interface_ports": [
|
|
"s00_couplers/M_AXI",
|
|
"xbar/S00_AXI"
|
|
]
|
|
},
|
|
"m00_couplers_to_axi_interconnect_0": {
|
|
"interface_ports": [
|
|
"M00_AXI",
|
|
"m00_couplers/M_AXI"
|
|
]
|
|
},
|
|
"xbar_to_m00_couplers": {
|
|
"interface_ports": [
|
|
"xbar/M00_AXI",
|
|
"m00_couplers/S_AXI"
|
|
]
|
|
},
|
|
"m01_couplers_to_axi_interconnect_0": {
|
|
"interface_ports": [
|
|
"M01_AXI",
|
|
"m01_couplers/M_AXI"
|
|
]
|
|
},
|
|
"m02_couplers_to_axi_interconnect_0": {
|
|
"interface_ports": [
|
|
"M02_AXI",
|
|
"m02_couplers/M_AXI"
|
|
]
|
|
},
|
|
"xbar_to_m01_couplers": {
|
|
"interface_ports": [
|
|
"xbar/M01_AXI",
|
|
"m01_couplers/S_AXI"
|
|
]
|
|
},
|
|
"m03_couplers_to_axi_interconnect_0": {
|
|
"interface_ports": [
|
|
"M03_AXI",
|
|
"m03_couplers/M_AXI"
|
|
]
|
|
},
|
|
"xbar_to_m02_couplers": {
|
|
"interface_ports": [
|
|
"xbar/M02_AXI",
|
|
"m02_couplers/S_AXI"
|
|
]
|
|
}
|
|
},
|
|
"nets": {
|
|
"axi_interconnect_0_ACLK_net": {
|
|
"ports": [
|
|
"ACLK",
|
|
"xbar/aclk",
|
|
"s00_couplers/S_ACLK",
|
|
"s00_couplers/M_ACLK",
|
|
"m00_couplers/M_ACLK",
|
|
"m01_couplers/M_ACLK",
|
|
"m02_couplers/M_ACLK",
|
|
"m03_couplers/M_ACLK",
|
|
"m00_couplers/S_ACLK",
|
|
"m01_couplers/S_ACLK",
|
|
"m02_couplers/S_ACLK",
|
|
"m03_couplers/S_ACLK"
|
|
]
|
|
},
|
|
"axi_interconnect_0_ARESETN_net": {
|
|
"ports": [
|
|
"ARESETN",
|
|
"xbar/aresetn",
|
|
"s00_couplers/S_ARESETN",
|
|
"s00_couplers/M_ARESETN",
|
|
"m00_couplers/M_ARESETN",
|
|
"m01_couplers/M_ARESETN",
|
|
"m02_couplers/M_ARESETN",
|
|
"m03_couplers/M_ARESETN",
|
|
"m00_couplers/S_ARESETN",
|
|
"m01_couplers/S_ARESETN",
|
|
"m02_couplers/S_ARESETN",
|
|
"m03_couplers/S_ARESETN"
|
|
]
|
|
}
|
|
}
|
|
},
|
|
"axi_single_spi_0": {
|
|
"vlnv": "xilinx.com:ip:axi_quad_spi:3.2",
|
|
"xci_name": "m3_for_xilinx_axi_single_spi_0_0",
|
|
"parameters": {
|
|
"C_FIFO_DEPTH": {
|
|
"value": "256"
|
|
},
|
|
"C_USE_STARTUP": {
|
|
"value": "0"
|
|
}
|
|
}
|
|
},
|
|
"axi_quad_spi_0": {
|
|
"vlnv": "xilinx.com:ip:axi_quad_spi:3.2",
|
|
"xci_name": "m3_for_xilinx_axi_quad_spi_0_0",
|
|
"parameters": {
|
|
"C_FIFO_DEPTH": {
|
|
"value": "256"
|
|
},
|
|
"C_SPI_MODE": {
|
|
"value": "2"
|
|
},
|
|
"C_USE_STARTUP": {
|
|
"value": "0"
|
|
}
|
|
}
|
|
},
|
|
"axi_xip_quad_spi_0": {
|
|
"vlnv": "xilinx.com:ip:axi_quad_spi:3.2",
|
|
"xci_name": "m3_for_xilinx_axi_xip_quad_spi_0_0",
|
|
"parameters": {
|
|
"C_SPI_MEMORY": {
|
|
"value": "3"
|
|
},
|
|
"C_SPI_MEM_ADDR_BITS": {
|
|
"value": "24"
|
|
},
|
|
"C_SPI_MODE": {
|
|
"value": "2"
|
|
},
|
|
"C_TYPE_OF_AXI4_INTERFACE": {
|
|
"value": "1"
|
|
},
|
|
"C_USE_STARTUP": {
|
|
"value": "0"
|
|
},
|
|
"C_XIP_MODE": {
|
|
"value": "1"
|
|
}
|
|
}
|
|
},
|
|
"axi_gpio_0": {
|
|
"vlnv": "xilinx.com:ip:axi_gpio:2.0",
|
|
"xci_name": "m3_for_xilinx_axi_gpio_0_0"
|
|
},
|
|
"axi_protocol_convert_0": {
|
|
"vlnv": "xilinx.com:ip:axi_protocol_converter:2.1",
|
|
"xci_name": "m3_for_xilinx_axi_protocol_convert_0_0"
|
|
},
|
|
"DAPLink_to_Arty_shield_0": {
|
|
"vlnv": "Arm.com:user:DAPLink_to_Arty_shield:1.0",
|
|
"xci_name": "m3_for_xilinx_DAPLink_to_Arty_shield_0_0"
|
|
}
|
|
},
|
|
"interface_nets": {
|
|
"axi_protocol_convert_0_M_AXI": {
|
|
"interface_ports": [
|
|
"axi_xip_quad_spi_0/AXI_FULL",
|
|
"axi_protocol_convert_0/M_AXI"
|
|
]
|
|
},
|
|
"C_AXI_1": {
|
|
"interface_ports": [
|
|
"C_AXI",
|
|
"axi_protocol_convert_0/S_AXI"
|
|
]
|
|
},
|
|
"axi_quad_spi_1_SPI_0": {
|
|
"interface_ports": [
|
|
"axi_quad_spi_0/SPI_0",
|
|
"DAPLink_to_Arty_shield_0/QSPI"
|
|
]
|
|
},
|
|
"axi_xip_quad_spi_0_SPI_0": {
|
|
"interface_ports": [
|
|
"DAPLink_to_Arty_shield_0/QSPI_XIP",
|
|
"axi_xip_quad_spi_0/SPI_0"
|
|
]
|
|
},
|
|
"axi_single_spi_0_SPI_0": {
|
|
"interface_ports": [
|
|
"axi_single_spi_0/SPI_0",
|
|
"DAPLink_to_Arty_shield_0/SPI"
|
|
]
|
|
},
|
|
"axi_interconnect_0_M00_AXI": {
|
|
"interface_ports": [
|
|
"axi_interconnect_0/M00_AXI",
|
|
"axi_xip_quad_spi_0/AXI_LITE"
|
|
]
|
|
},
|
|
"axi_interconnect_0_M03_AXI": {
|
|
"interface_ports": [
|
|
"axi_interconnect_0/M03_AXI",
|
|
"axi_quad_spi_0/AXI_LITE"
|
|
]
|
|
},
|
|
"DAPLink_to_Arty_shie_1_UART": {
|
|
"interface_ports": [
|
|
"UART_out",
|
|
"DAPLink_to_Arty_shield_0/UART_out"
|
|
]
|
|
},
|
|
"axi_interconnect_0_M01_AXI": {
|
|
"interface_ports": [
|
|
"axi_interconnect_0/M01_AXI",
|
|
"axi_gpio_0/S_AXI"
|
|
]
|
|
},
|
|
"axi_interconnect_0_M02_AXI": {
|
|
"interface_ports": [
|
|
"axi_interconnect_0/M02_AXI",
|
|
"axi_single_spi_0/AXI_LITE"
|
|
]
|
|
},
|
|
"S_AXI_1": {
|
|
"interface_ports": [
|
|
"S_AXI",
|
|
"axi_interconnect_0/S00_AXI"
|
|
]
|
|
},
|
|
"DAPLink_to_Arty_shie_1_shield": {
|
|
"interface_ports": [
|
|
"Shield_out",
|
|
"DAPLink_to_Arty_shield_0/shield"
|
|
]
|
|
}
|
|
},
|
|
"nets": {
|
|
"s_axi_aclk_1": {
|
|
"ports": [
|
|
"s_axi_aclk",
|
|
"axi_single_spi_0/s_axi_aclk",
|
|
"axi_quad_spi_0/s_axi_aclk",
|
|
"axi_xip_quad_spi_0/s_axi_aclk",
|
|
"axi_gpio_0/s_axi_aclk",
|
|
"axi_xip_quad_spi_0/s_axi4_aclk",
|
|
"axi_protocol_convert_0/aclk",
|
|
"axi_interconnect_0/ACLK",
|
|
"axi_interconnect_0/S00_ACLK",
|
|
"axi_interconnect_0/M00_ACLK",
|
|
"axi_interconnect_0/M01_ACLK",
|
|
"axi_interconnect_0/M02_ACLK",
|
|
"axi_interconnect_0/M03_ACLK"
|
|
]
|
|
},
|
|
"s_axi_aresetn_1": {
|
|
"ports": [
|
|
"s_axi_aresetn",
|
|
"axi_single_spi_0/s_axi_aresetn",
|
|
"axi_quad_spi_0/s_axi_aresetn",
|
|
"axi_xip_quad_spi_0/s_axi_aresetn",
|
|
"axi_gpio_0/s_axi_aresetn",
|
|
"axi_xip_quad_spi_0/s_axi4_aresetn",
|
|
"axi_protocol_convert_0/aresetn",
|
|
"axi_interconnect_0/ARESETN",
|
|
"axi_interconnect_0/S00_ARESETN",
|
|
"axi_interconnect_0/M00_ARESETN",
|
|
"axi_interconnect_0/M01_ARESETN",
|
|
"axi_interconnect_0/M02_ARESETN",
|
|
"axi_interconnect_0/M03_ARESETN"
|
|
]
|
|
},
|
|
"DAPLink_to_Arty_shie_1_DAPLink_fittedn": {
|
|
"ports": [
|
|
"DAPLink_to_Arty_shield_0/DAPLink_fittedn",
|
|
"DAPLink_fittedn"
|
|
]
|
|
},
|
|
"DAPLink_to_Arty_shie_1_uart_rxd_axi": {
|
|
"ports": [
|
|
"DAPLink_to_Arty_shield_0/uart_rxd_axi",
|
|
"uart_rxd_axi"
|
|
]
|
|
},
|
|
"DAPLink_to_Arty_shie_1_SWDI": {
|
|
"ports": [
|
|
"DAPLink_to_Arty_shield_0/SWDI",
|
|
"SWDI"
|
|
]
|
|
},
|
|
"DAPLink_to_Arty_shie_1_SWCLK": {
|
|
"ports": [
|
|
"DAPLink_to_Arty_shield_0/SWCLK",
|
|
"SWCLK"
|
|
]
|
|
},
|
|
"DAPLink_to_Arty_shie_1_SWRSTn": {
|
|
"ports": [
|
|
"DAPLink_to_Arty_shield_0/SWRSTn",
|
|
"nSRST"
|
|
]
|
|
},
|
|
"uart_txd_axi_1": {
|
|
"ports": [
|
|
"uart_txd_axi",
|
|
"DAPLink_to_Arty_shield_0/uart_txd_axi"
|
|
]
|
|
},
|
|
"ext_spi_clk_1": {
|
|
"ports": [
|
|
"ext_spi_clk",
|
|
"axi_single_spi_0/ext_spi_clk",
|
|
"axi_quad_spi_0/ext_spi_clk",
|
|
"axi_xip_quad_spi_0/ext_spi_clk",
|
|
"DAPLink_to_Arty_shield_0/ext_spi_clk"
|
|
]
|
|
},
|
|
"axi_quad_spi_1_ip2intc_irpt": {
|
|
"ports": [
|
|
"axi_quad_spi_0/ip2intc_irpt",
|
|
"qspi_irq"
|
|
]
|
|
},
|
|
"axi_single_spi_0_ip2intc_irpt": {
|
|
"ports": [
|
|
"axi_single_spi_0/ip2intc_irpt",
|
|
"spi_irq"
|
|
]
|
|
},
|
|
"axi_gpio_0_gpio_io_o": {
|
|
"ports": [
|
|
"axi_gpio_0/gpio_io_o",
|
|
"DAPLink_to_Arty_shield_0/qspi_sel"
|
|
]
|
|
},
|
|
"axi_xip_quad_spi_0_ip2intc_irpt": {
|
|
"ports": [
|
|
"axi_xip_quad_spi_0/ip2intc_irpt",
|
|
"qspi_xip_irq"
|
|
]
|
|
},
|
|
"SWDO_1": {
|
|
"ports": [
|
|
"SWDO",
|
|
"DAPLink_to_Arty_shield_0/SWDO"
|
|
]
|
|
},
|
|
"SWDOEN_1": {
|
|
"ports": [
|
|
"SWDOEN",
|
|
"DAPLink_to_Arty_shield_0/SWDOEN"
|
|
]
|
|
}
|
|
}
|
|
},
|
|
"xlconcat_0": {
|
|
"vlnv": "xilinx.com:ip:xlconcat:2.1",
|
|
"xci_name": "m3_for_xilinx_xlconcat_0_0",
|
|
"parameters": {
|
|
"NUM_PORTS": {
|
|
"value": "8"
|
|
}
|
|
}
|
|
},
|
|
"xlconcat_1": {
|
|
"vlnv": "xilinx.com:ip:xlconcat:2.1",
|
|
"xci_name": "m3_for_xilinx_xlconcat_1_0",
|
|
"parameters": {
|
|
"IN6_WIDTH": {
|
|
"value": "25"
|
|
},
|
|
"NUM_PORTS": {
|
|
"value": "2"
|
|
}
|
|
}
|
|
},
|
|
"xlconstant_1": {
|
|
"vlnv": "xilinx.com:ip:xlconstant:1.1",
|
|
"xci_name": "m3_for_xilinx_xlconstant_1_0",
|
|
"parameters": {
|
|
"CONST_VAL": {
|
|
"value": "1"
|
|
},
|
|
"CONST_WIDTH": {
|
|
"value": "1"
|
|
}
|
|
}
|
|
},
|
|
"Cortex_M3_0": {
|
|
"vlnv": "Arm.com:CortexM:CORTEXM3_AXI:1.1",
|
|
"xci_name": "m3_for_xilinx_Cortex_M3_0_0",
|
|
"parameters": {
|
|
"Component_Name": {
|
|
"value": "m3_for_arty_a7_Cortex_M3_0_0"
|
|
},
|
|
"DEBUG_LVL": {
|
|
"value": "2"
|
|
},
|
|
"DTCM_SIZE": {
|
|
"value": "\"0110\""
|
|
},
|
|
"ITCM_INIT_FILE": {
|
|
"value": "bram_a7.hex"
|
|
},
|
|
"ITCM_SIZE": {
|
|
"value": "\"0110\""
|
|
},
|
|
"JTAG_PRESENT": {
|
|
"value": "false"
|
|
},
|
|
"TRACE_LVL": {
|
|
"value": "0"
|
|
},
|
|
"WIC_PRESENT": {
|
|
"value": "false"
|
|
}
|
|
}
|
|
},
|
|
"clk_wiz": {
|
|
"vlnv": "xilinx.com:ip:clk_wiz:6.0",
|
|
"xci_name": "m3_for_xilinx_clk_wiz_0",
|
|
"parameters": {
|
|
"CLKIN1_JITTER_PS": {
|
|
"value": "200.0"
|
|
},
|
|
"CLKOUT1_JITTER": {
|
|
"value": "192.113"
|
|
},
|
|
"CLKOUT1_PHASE_ERROR": {
|
|
"value": "164.985"
|
|
},
|
|
"CLKOUT1_REQUESTED_OUT_FREQ": {
|
|
"value": "50.000"
|
|
},
|
|
"MMCM_CLKFBOUT_MULT_F": {
|
|
"value": "20.000"
|
|
},
|
|
"MMCM_CLKIN1_PERIOD": {
|
|
"value": "20.000"
|
|
},
|
|
"MMCM_CLKIN2_PERIOD": {
|
|
"value": "10.0"
|
|
},
|
|
"MMCM_CLKOUT0_DIVIDE_F": {
|
|
"value": "20.000"
|
|
},
|
|
"MMCM_DIVCLK_DIVIDE": {
|
|
"value": "1"
|
|
},
|
|
"PRIM_IN_FREQ": {
|
|
"value": "50.000"
|
|
},
|
|
"RESET_PORT": {
|
|
"value": "resetn"
|
|
},
|
|
"RESET_TYPE": {
|
|
"value": "ACTIVE_LOW"
|
|
}
|
|
}
|
|
},
|
|
"rst_clk_wiz_100M": {
|
|
"vlnv": "xilinx.com:ip:proc_sys_reset:5.0",
|
|
"xci_name": "m3_for_xilinx_rst_clk_wiz_100M_0"
|
|
},
|
|
"axi_gpio_0": {
|
|
"vlnv": "xilinx.com:ip:axi_gpio:2.0",
|
|
"xci_name": "m3_for_xilinx_axi_gpio_0_1",
|
|
"parameters": {
|
|
"C_GPIO_WIDTH": {
|
|
"value": "4"
|
|
},
|
|
"C_INTERRUPT_PRESENT": {
|
|
"value": "1"
|
|
},
|
|
"USE_BOARD_FLOW": {
|
|
"value": "true"
|
|
}
|
|
}
|
|
},
|
|
"axi_gpio_1": {
|
|
"vlnv": "xilinx.com:ip:axi_gpio:2.0",
|
|
"xci_name": "m3_for_xilinx_axi_gpio_1_0",
|
|
"parameters": {
|
|
"C_GPIO_WIDTH": {
|
|
"value": "4"
|
|
},
|
|
"C_INTERRUPT_PRESENT": {
|
|
"value": "1"
|
|
},
|
|
"USE_BOARD_FLOW": {
|
|
"value": "true"
|
|
}
|
|
}
|
|
},
|
|
"axi_quad_spi_0": {
|
|
"vlnv": "xilinx.com:ip:axi_quad_spi:3.2",
|
|
"xci_name": "m3_for_xilinx_axi_quad_spi_0_1",
|
|
"parameters": {
|
|
"C_FIFO_DEPTH": {
|
|
"value": "256"
|
|
},
|
|
"C_USE_STARTUP": {
|
|
"value": "0"
|
|
}
|
|
}
|
|
}
|
|
},
|
|
"interface_nets": {
|
|
"axi_interconnect_0_M04_AXI": {
|
|
"interface_ports": [
|
|
"axi_interconnect_0/M04_AXI",
|
|
"axi_quad_spi_0/AXI_LITE"
|
|
]
|
|
},
|
|
"qspi_flash": {
|
|
"interface_ports": [
|
|
"qspi_flash",
|
|
"axi_quad_spi_0/SPI_0"
|
|
]
|
|
},
|
|
"axi_interconnect_0_M01_AXI": {
|
|
"interface_ports": [
|
|
"axi_gpio_0/S_AXI",
|
|
"axi_interconnect_0/M01_AXI"
|
|
]
|
|
},
|
|
"axi_gpio_1_GPIO": {
|
|
"interface_ports": [
|
|
"LED_4bit",
|
|
"axi_gpio_1/GPIO"
|
|
]
|
|
},
|
|
"V2C_DAPLink_interface_Shield_out": {
|
|
"interface_ports": [
|
|
"DAPLink",
|
|
"daplink_if_0/Shield_out"
|
|
]
|
|
},
|
|
"S_AXI_1": {
|
|
"interface_ports": [
|
|
"daplink_if_0/S_AXI",
|
|
"axi_interconnect_0/M05_AXI"
|
|
]
|
|
},
|
|
"axi_interconnect_0_M03_AXI": {
|
|
"interface_ports": [
|
|
"axi_bram_ctrl_0/S_AXI",
|
|
"axi_interconnect_0/M03_AXI"
|
|
]
|
|
},
|
|
"V2C_DAPLink_interface_UART_out": {
|
|
"interface_ports": [
|
|
"usb_uart",
|
|
"daplink_if_0/UART_out"
|
|
]
|
|
},
|
|
"axi_gpio_0_GPIO": {
|
|
"interface_ports": [
|
|
"key_4bit",
|
|
"axi_gpio_0/GPIO"
|
|
]
|
|
},
|
|
"Cortex_M3_0_CM3_SYS_AXI3": {
|
|
"interface_ports": [
|
|
"Cortex_M3_0/CM3_SYS_AXI3",
|
|
"axi_interconnect_0/S00_AXI"
|
|
]
|
|
},
|
|
"axi_bram_ctrl_0_BRAM_PORTA": {
|
|
"interface_ports": [
|
|
"axi_bram_ctrl_0/BRAM_PORTA",
|
|
"blk_mem_gen_0/BRAM_PORTA"
|
|
]
|
|
},
|
|
"axi_interconnect_0_M02_AXI": {
|
|
"interface_ports": [
|
|
"axi_interconnect_0/M02_AXI",
|
|
"axi_gpio_1/S_AXI"
|
|
]
|
|
},
|
|
"axi_interconnect_0_M00_AXI": {
|
|
"interface_ports": [
|
|
"axi_uartlite_0/S_AXI",
|
|
"axi_interconnect_0/M00_AXI"
|
|
]
|
|
},
|
|
"Cortex_M3_0_CM3_CODE_AXI3": {
|
|
"interface_ports": [
|
|
"Cortex_M3_0/CM3_CODE_AXI3",
|
|
"daplink_if_0/C_AXI"
|
|
]
|
|
}
|
|
},
|
|
"nets": {
|
|
"V2C_DAPLink_interface_DAPLink_fittedn": {
|
|
"ports": [
|
|
"daplink_if_0/DAPLink_fittedn",
|
|
"xlconcat_1/In0",
|
|
"xlconcat_0/In7"
|
|
]
|
|
},
|
|
"V2C_DAPLink_interface_qspi_irq": {
|
|
"ports": [
|
|
"daplink_if_0/qspi_irq",
|
|
"xlconcat_0/In4"
|
|
]
|
|
},
|
|
"V2C_DAPLink_interface_qspi_xip_irq": {
|
|
"ports": [
|
|
"daplink_if_0/qspi_xip_irq",
|
|
"xlconcat_0/In6"
|
|
]
|
|
},
|
|
"V2C_DAPLink_interface_spi_irq": {
|
|
"ports": [
|
|
"daplink_if_0/spi_irq",
|
|
"xlconcat_0/In5"
|
|
]
|
|
},
|
|
"V2C_DAPLink_interface_uart_rxd_axi": {
|
|
"ports": [
|
|
"daplink_if_0/uart_rxd_axi",
|
|
"axi_uartlite_0/rx"
|
|
]
|
|
},
|
|
"axi_uartlite_0_interrupt": {
|
|
"ports": [
|
|
"axi_uartlite_0/interrupt",
|
|
"xlconcat_0/In0"
|
|
]
|
|
},
|
|
"axi_uartlite_0_tx": {
|
|
"ports": [
|
|
"axi_uartlite_0/tx",
|
|
"daplink_if_0/uart_txd_axi"
|
|
]
|
|
},
|
|
"clk_wiz_0_clk_out1": {
|
|
"ports": [
|
|
"clk_wiz/clk_out1",
|
|
"axi_bram_ctrl_0/s_axi_aclk",
|
|
"axi_uartlite_0/s_axi_aclk",
|
|
"axi_interconnect_0/ACLK",
|
|
"axi_interconnect_0/S00_ACLK",
|
|
"axi_interconnect_0/M00_ACLK",
|
|
"axi_interconnect_0/M01_ACLK",
|
|
"axi_interconnect_0/M02_ACLK",
|
|
"axi_interconnect_0/M03_ACLK",
|
|
"axi_interconnect_0/M04_ACLK",
|
|
"daplink_if_0/s_axi_aclk",
|
|
"axi_interconnect_0/M05_ACLK",
|
|
"Cortex_M3_0/HCLK",
|
|
"rst_clk_wiz_100M/slowest_sync_clk",
|
|
"axi_gpio_0/s_axi_aclk",
|
|
"axi_gpio_1/s_axi_aclk",
|
|
"axi_quad_spi_0/s_axi_aclk",
|
|
"axi_quad_spi_0/ext_spi_clk",
|
|
"daplink_if_0/ext_spi_clk"
|
|
]
|
|
},
|
|
"xlconstant_1_dout": {
|
|
"ports": [
|
|
"xlconstant_1/dout",
|
|
"xlconcat_1/In1"
|
|
]
|
|
},
|
|
"xlconcat_0_dout": {
|
|
"ports": [
|
|
"xlconcat_0/dout",
|
|
"Cortex_M3_0/IRQ"
|
|
]
|
|
},
|
|
"xlconcat_1_dout": {
|
|
"ports": [
|
|
"xlconcat_1/dout",
|
|
"Cortex_M3_0/CFGITCMEN"
|
|
]
|
|
},
|
|
"CortexM3DbgAXI_0_SWDOEN": {
|
|
"ports": [
|
|
"Cortex_M3_0/SWDOEN",
|
|
"daplink_if_0/SWDOEN"
|
|
]
|
|
},
|
|
"CortexM3DbgAXI_0_SWDO": {
|
|
"ports": [
|
|
"Cortex_M3_0/SWDO",
|
|
"daplink_if_0/SWDO"
|
|
]
|
|
},
|
|
"daplink_if_0_SWCLK": {
|
|
"ports": [
|
|
"daplink_if_0/SWCLK",
|
|
"Cortex_M3_0/SWCLKTCK"
|
|
]
|
|
},
|
|
"daplink_if_0_SWDI": {
|
|
"ports": [
|
|
"daplink_if_0/SWDI",
|
|
"Cortex_M3_0/SWDITMS"
|
|
]
|
|
},
|
|
"clk_wiz_locked": {
|
|
"ports": [
|
|
"clk_wiz/locked",
|
|
"rst_clk_wiz_100M/dcm_locked"
|
|
]
|
|
},
|
|
"rst_clk_wiz_100M_peripheral_aresetn": {
|
|
"ports": [
|
|
"rst_clk_wiz_100M/peripheral_aresetn",
|
|
"axi_bram_ctrl_0/s_axi_aresetn",
|
|
"axi_uartlite_0/s_axi_aresetn",
|
|
"daplink_if_0/s_axi_aresetn",
|
|
"axi_interconnect_0/S00_ARESETN",
|
|
"axi_interconnect_0/M00_ARESETN",
|
|
"axi_interconnect_0/M01_ARESETN",
|
|
"axi_interconnect_0/M02_ARESETN",
|
|
"axi_interconnect_0/M03_ARESETN",
|
|
"axi_interconnect_0/M04_ARESETN",
|
|
"axi_interconnect_0/M05_ARESETN",
|
|
"axi_interconnect_0/ARESETN",
|
|
"Cortex_M3_0/SYSRESETn",
|
|
"axi_gpio_0/s_axi_aresetn",
|
|
"axi_gpio_1/s_axi_aresetn",
|
|
"axi_quad_spi_0/s_axi_aresetn"
|
|
]
|
|
},
|
|
"clk_50MHz": {
|
|
"ports": [
|
|
"clk_50MHz",
|
|
"clk_wiz/clk_in1"
|
|
]
|
|
},
|
|
"sys_rst_n": {
|
|
"ports": [
|
|
"sys_rst_n",
|
|
"rst_clk_wiz_100M/ext_reset_in",
|
|
"clk_wiz/resetn"
|
|
]
|
|
},
|
|
"axi_gpio_0_ip2intc_irpt": {
|
|
"ports": [
|
|
"axi_gpio_0/ip2intc_irpt",
|
|
"xlconcat_0/In1"
|
|
]
|
|
},
|
|
"axi_gpio_1_ip2intc_irpt": {
|
|
"ports": [
|
|
"axi_gpio_1/ip2intc_irpt",
|
|
"xlconcat_0/In2"
|
|
]
|
|
},
|
|
"axi_quad_spi_0_ip2intc_irpt": {
|
|
"ports": [
|
|
"axi_quad_spi_0/ip2intc_irpt",
|
|
"xlconcat_0/In3"
|
|
]
|
|
}
|
|
},
|
|
"addressing": {
|
|
"/Cortex_M3_0": {
|
|
"address_spaces": {
|
|
"CM3_SYS_AXI3": {
|
|
"range": "4G",
|
|
"width": "32",
|
|
"segments": {
|
|
"SEG_axi_bram_ctrl_0_Mem0": {
|
|
"address_block": "/axi_bram_ctrl_0/S_AXI/Mem0",
|
|
"offset": "0x60000000",
|
|
"range": "8K"
|
|
},
|
|
"SEG_axi_gpio_0_Reg": {
|
|
"address_block": "/axi_gpio_0/S_AXI/Reg",
|
|
"offset": "0x40110000",
|
|
"range": "64K"
|
|
},
|
|
"SEG_axi_gpio_0_Reg1": {
|
|
"address_block": "/daplink_if_0/axi_gpio_0/S_AXI/Reg",
|
|
"offset": "0x40010000",
|
|
"range": "64K"
|
|
},
|
|
"SEG_axi_gpio_1_Reg": {
|
|
"address_block": "/axi_gpio_1/S_AXI/Reg",
|
|
"offset": "0x40120000",
|
|
"range": "64K"
|
|
},
|
|
"SEG_axi_quad_spi_0_Reg": {
|
|
"address_block": "/axi_quad_spi_0/AXI_LITE/Reg",
|
|
"offset": "0x40130000",
|
|
"range": "64K"
|
|
},
|
|
"SEG_axi_quad_spi_0_Reg1": {
|
|
"address_block": "/daplink_if_0/axi_quad_spi_0/AXI_LITE/Reg",
|
|
"offset": "0x40020000",
|
|
"range": "64K"
|
|
},
|
|
"SEG_axi_single_spi_0_Reg": {
|
|
"address_block": "/daplink_if_0/axi_single_spi_0/AXI_LITE/Reg",
|
|
"offset": "0x40030000",
|
|
"range": "64K"
|
|
},
|
|
"SEG_axi_uartlite_0_Reg": {
|
|
"address_block": "/axi_uartlite_0/S_AXI/Reg",
|
|
"offset": "0x40100000",
|
|
"range": "64K"
|
|
},
|
|
"SEG_axi_xip_quad_spi_0_Reg": {
|
|
"address_block": "/daplink_if_0/axi_xip_quad_spi_0/AXI_LITE/Reg",
|
|
"offset": "0x40000000",
|
|
"range": "64K"
|
|
}
|
|
}
|
|
},
|
|
"CM3_CODE_AXI3": {
|
|
"range": "4G",
|
|
"width": "32",
|
|
"segments": {
|
|
"SEG_axi_xip_quad_spi_0_MEM0": {
|
|
"address_block": "/daplink_if_0/axi_xip_quad_spi_0/aximm/MEM0",
|
|
"offset": "0x00000000",
|
|
"range": "1M"
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
} |