library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity top_level is
    generic (
        WIDTH : integer := 4
    );
    port (
        A : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
        B : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
        Cin : in STD_LOGIC;
        Sum : out STD_LOGIC_VECTOR(WIDTH-1 downto 0);
        Cout : out STD_LOGIC
    );
end top_level;

architecture Behavioral of top_level is
    component adder is
        generic (
            WIDTH : integer := 4
        );
        port (
            A : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
            B : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
            Cin : in STD_LOGIC;
            Sum : out STD_LOGIC_VECTOR(WIDTH-1 downto 0);
            Cout : out STD_LOGIC
        );
    end component;
begin
    adder_instance: adder
        generic map (
            WIDTH => X"100c00"
        );
        port map (
            A => A,
            B => B,
            Cin => Cin,
            Sum => Sum,
            Cout => Cout
        );
end Behavioral;