// Test Scenario to validate correct translation
// Refer: https://github.com/Nic30/hdlConvertor/issues/173
`define ADD 64
module dummy #(
    parameter reg ADDR_WIDTH = 4,
    parameter interger ADDER_OOO = 25,
    parameter [63:0] ADDER_OOO_1 = (1 << ADDER_OOO) + 1,
    parameter logic [63:0] ADD_OTHER = `ADD'hff1
) (c, a, b, d, f);
    output reg c;
    output logic [61:0] f;
    input [ADDR_WIDTH_ANSI - 1:0] d;
    input a, b;
    and a1(c, a, b);
endmodule

module d2(y, a);
    output [3:0] y;
    input reg [2:0] a;

    not n1 (y, a);
endmodule

module example (a, b, c, d);
    input a, b, c;
    output d;

    wire tmp;
    wire tmp2;
    wire tmp3;
    and a1 (tmp, a, b);
    dummy du(
        .c(tmp2), .a(b), .b(c));
    dummy #(
        .ADDR_WIDTH(8)
    ) duu(tmp3, b, c);
    or o1 (d, tmp, tmp2);
endmodule

// test dummy comment
module dummy_ansi #(
    parameter ADDR_WIDTH = 4,
    parameter interger ADDER_OOO = 25,
    parameter [63:0] ADDER_OOO_1 = (1 << ADDER_OOO) + 1,
    parameter logic [63:0] ADD_OTHER = `ADD'hff1
) (
    output [ADDR_WIDTH_ANSI - 1:0] c,
    input [ADDR_WIDTH_ANSI-1: 0] a,
    input [ADDR_WIDTH_ANSI-1:0] b
);
    and a1(c, a, b);
    assign c = a & b;
endmodule

module d2_ansi(
    output [3:0] y,
    input reg [2:0] a
);

    not n1 (y, a);
endmodule

module example_ansi (
    input a, b, c,
    output d
);

    wire tmp;
    wire tmp2;
    wire tmp3;
    and a1 (tmp, a, b);
    dummy_ansi du_ansi(
        .c(tmp2), .b(b), .a(c));
    dummy_ansi #(
        .ADDR_WIDTH_ANSI(8)
    ) duu_ansi(
        tmp3, 
        b, 
        c
    );
    or o1 (d, tmp, tmp2);
endmodule
