change vhdl parse: only think of entity as module

This commit is contained in:
light-ly 2024-11-16 10:08:13 +08:00
parent 9bb54e0327
commit 0aa6ef0462

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@ -143,47 +143,48 @@ fn parse_tokens(tokens: Vec<Token>) -> Vec<Module> {
} }
"architecture" => { "architecture" => {
if (i >= 1 as usize) && (kind_str(tokens[i-1].kind) != "end") || (i < 1) { if (i >= 1 as usize) && (kind_str(tokens[i-1].kind) != "end") || (i < 1) {
let name = get_value(&tokens[i+3]); // !!! We not think of Architecture as VHDL Module Now
if let None = modules.iter().find(|module| module.name == name) { // let name = get_value(&tokens[i+3]);
let start_pos = tokens[i].pos.range.start; // if let None = modules.iter().find(|module| module.name == name) {
i += 1; // let start_pos = tokens[i].pos.range.start;
let arch_name = get_value(&tokens[i]); // i += 1;
// println!("arch name {:?}", arch_name); // let arch_name = get_value(&tokens[i]);
let mut end = i; // // println!("arch name {:?}", arch_name);
while (end+1 < tokens.len()) && // let mut end = i;
!(kind_str(tokens[end].kind) == "end" && // while (end+1 < tokens.len()) &&
(kind_str(tokens[end+1].kind) == "architecture" || get_value(&tokens[end+1]) == arch_name)) { // !(kind_str(tokens[end].kind) == "end" &&
end += 1; // (kind_str(tokens[end+1].kind) == "architecture" || get_value(&tokens[end+1]) == arch_name)) {
} // end += 1;
let end_pos = if end+1 < tokens.len() && get_value(&tokens[end+1]) == arch_name { // }
// i = end + 2; // let end_pos = if end+1 < tokens.len() && get_value(&tokens[end+1]) == arch_name {
tokens[end+2].pos.range.end // // i = end + 2;
} else if end + 3 < tokens.len() { // tokens[end+2].pos.range.end
// i = end + 3; // } else if end + 3 < tokens.len() {
tokens[end+3].pos.range.end // // i = end + 3;
} else { // tokens[end+3].pos.range.end
// i = end; // } else {
tokens[end].pos.range.end // // i = end;
}; // tokens[end].pos.range.end
let module = Module { // };
name: name.to_string(), // let module = Module {
params: Vec::new(), // name: name.to_string(),
ports: Vec::new(), // params: Vec::new(),
instances: Vec::new(), // ports: Vec::new(),
range: Range { // instances: Vec::new(),
start: Position { // range: Range {
line: start_pos.line + 1, // start: Position {
character: start_pos.character + 1 // line: start_pos.line + 1,
}, // character: start_pos.character + 1
end: Position { // },
line: end_pos.line + 1, // end: Position {
character: end_pos.character + 1 // line: end_pos.line + 1,
} // character: end_pos.character + 1
} // }
}; // }
last_module_name = name.to_string(); // };
modules.push(module); // last_module_name = name.to_string();
} // modules.push(module);
// }
} }
} }
"configuration" => { "configuration" => {