From 3bdd7272679b53b3daf881c0e6281f2ec9f2b8f1 Mon Sep 17 00:00:00 2001
From: light-ly <l136665@163.com>
Date: Tue, 10 Dec 2024 00:08:46 +0800
Subject: [PATCH] fix vhdl project init

---
 src/server.rs  |  2 ++
 src/sources.rs | 27 +++++++++++++++++++++++++++
 2 files changed, 29 insertions(+)

diff --git a/src/server.rs b/src/server.rs
index 6935001..63a8a31 100644
--- a/src/server.rs
+++ b/src/server.rs
@@ -161,6 +161,8 @@ impl LanguageServer for Backend {
             &configure.extension_path
         );
 
+        self.server.srcs.init_vhdl_project(&configure.extension_path);
+
         // 初始化系统缓存路径
         self.server.cache.start(&version);
 
diff --git a/src/sources.rs b/src/sources.rs
index d9e745c..1d6f7b8 100644
--- a/src/sources.rs
+++ b/src/sources.rs
@@ -282,6 +282,33 @@ impl Sources {
         }
     }
 
+    pub fn init_vhdl_project(&self, extension_path: &str) {
+        let project_handle = self.vhdl_project.clone();
+        let mut global_project = project_handle.write().unwrap();
+        match &mut *global_project {
+            Some(_) => (),
+            None => {
+                let std_cfg_path = match PathBuf::from_str(&(extension_path.to_string() + "/resources/dide-lsp/static/vhdl_std_lib/vhdl_ls.toml")) {
+                    Ok(path) => path,
+                    Err(e) => {
+                        info!("error happen in <vhdl_parse_pipeline>: {:?}", e);
+                        return;
+                    }
+                };
+                match vhdl_lang::Config::read_file_path(&std_cfg_path) {
+                    Ok(std_config) => {
+                        let mut messages = Vec::new();
+                        let mut project = Project::from_config(std_config.clone(), &mut messages);
+                        project.analyse();
+                        let config_file_strs = Vec::new();
+                        *global_project = Some(VhdlProject { project, std_config, config_file_strs });
+                    }
+                    Err(e) => info!("error happen in <init_vhdl_project>: Can't load standard vhdl lib from {std_cfg_path:#?} because {e:#?}")
+                }
+            }
+        }
+    }
+
     /// 增加一个 hdl 文件，并为该文件添加单独的解析线程
     pub fn add(&self, server: &LspServer, doc: TextDocumentItem) {
         // 对于当前的文件增加一个解析线程，不断进行解析和同步