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add multi files support to vhdl

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This commit is contained in:
light-ly 2024-10-04 21:30:56 +08:00
parent 1b93b42a90
commit 466fad9296
7 changed files with 17 additions and 33 deletions
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2
rust_hdl

@ -1 +1 @@
Subproject commit 47686dd663b8fd063f4064fea012088a89f7aeb3
Subproject commit 69fba9af8cb981ce1aaeacd20ca74771f12d9aa1

8
src/completion/vhdl.rs
View File

@ -23,12 +23,8 @@ pub fn completion(server: &LSPServer, params: &CompletionParams) -> Option<Compl
}
};
let escape_path = to_escape_path(&path);
let escape_path_string = escape_path.to_str().unwrap_or("");
if escape_path_string.len() == 0 {
info!("error happen in [vhdl_parser_pipeline], escape_path_string is empty");
return None;
}
let project = match projects.get(escape_path_string) {
let project = match projects.get("VHDL_Project") {
Some(project) => project,
None => return None
};

8
src/definition/vhdl.rs
View File

@ -19,12 +19,8 @@ pub fn goto_vhdl_definition(server: &LSPServer, params: &GotoDefinitionParams) -
}
};
let escape_path = to_escape_path(&path);
let escape_path_string = escape_path.to_str().unwrap_or("");
if escape_path_string.len() == 0 {
info!("error happen in [vhdl_parser_pipeline], escape_path_string is empty");
return None;
}
let project = match projects.get(escape_path_string) {
let project = match projects.get("VHDL_Project") {
Some(project) => project,
None => return None
};

8
src/document_highlight/vhdl.rs
View File

@ -22,12 +22,8 @@ pub fn vhdl_document_highlight(
}
};
let escape_path = to_escape_path(&path);
let escape_path_string = escape_path.to_str().unwrap_or("");
if escape_path_string.len() == 0 {
info!("error happen in [vhdl_parser_pipeline], escape_path_string is empty");
return None;
}
let project = match projects.get(escape_path_string) {
let project = match projects.get("VHDL_Project") {
Some(project) => project,
None => return None
};

8
src/document_symbol/vhdl.rs
View File

@ -21,12 +21,8 @@ pub fn vhdl_document_symbol(server: &LSPServer, params: &DocumentSymbolParams) -
}
};
let escape_path = to_escape_path(&path);
let escape_path_string = escape_path.to_str().unwrap_or("");
if escape_path_string.len() == 0 {
info!("error happen in [vhdl_parser_pipeline], escape_path_string is empty");
return None;
}
let project = match projects.get(escape_path_string) {
let project = match projects.get("VHDL_Project") {
Some(project) => project,
None => return None
};

8
src/hover/vhdl.rs
View File

@ -21,12 +21,8 @@ pub fn hover(server: &LSPServer, params: &HoverParams) -> Option<Hover> {
}
};
let escape_path = to_escape_path(&path);
let escape_path_string = escape_path.to_str().unwrap_or("");
if escape_path_string.len() == 0 {
info!("error happen in [vhdl_parser_pipeline], escape_path_string is empty");
return None;
}
let project = match projects.get(escape_path_string) {
let project = match projects.get("VHDL_Project") {
Some(project) => project,
None => return None
};

6
src/sources.rs
View File

@ -624,8 +624,12 @@ pub fn vhdl_parser_pipeline(
hdl_param_handle.update_fast(escape_path_string.to_string(), fast);
}
let mut msg_printer = MessagePrinter::default();
if let Some(project) = design_files.get_mut("VHDLProject") {
project.add_file(&escape_path, &mut msg_printer);
} else {
let project = vhdl_lang::Project::new_without_config(&escape_path, &mut msg_printer, None);
design_files.insert(escape_path_string.to_string(), project);
design_files.insert("VHDL_Project".to_string(), project);
}
}
}