From 8e2b3737029d2401025055eb8044fe33db9211d2 Mon Sep 17 00:00:00 2001
From: LSTM-Kirigaya <1193466151@qq.com>
Date: Wed, 4 Dec 2024 17:50:42 +0800
Subject: [PATCH] =?UTF-8?q?=E6=B7=BB=E5=8A=A0=2018.3.3=20=E6=A0=87?=
 =?UTF-8?q?=E5=87=86?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 src/completion/keyword.rs    |   2 +-
 src/completion/sys_tasks.rs  | 491 +++++++++++++++++++----------------
 src/diagnostics/mod.rs       |  28 +-
 src/diagnostics/modelsim.rs  |   5 +
 src/diagnostics/verible.rs   |  49 ++++
 src/diagnostics/verilator.rs |  33 +++
 src/diagnostics/vivado.rs    |  28 ++
 src/format/mod.rs            |   4 +-
 src/server.rs                | 105 ++------
 src/sources.rs               |   6 +-
 10 files changed, 430 insertions(+), 321 deletions(-)

diff --git a/src/completion/keyword.rs b/src/completion/keyword.rs
index 7a448cd..09acc90 100644
--- a/src/completion/keyword.rs
+++ b/src/completion/keyword.rs
@@ -135,7 +135,7 @@ pub const VLOG_KEYWORDS: &[(&str, &str)] = &[
     ("import", ""),
     ("incdir", ""),
     ("include", "`include \"$1\""),
-    ("initial", ""),
+    ("initial", "initial begin\n\t$1\nend"),
     ("inout", ""),
     ("input", ""),
     ("inside", ""),
diff --git a/src/completion/sys_tasks.rs b/src/completion/sys_tasks.rs
index a171035..f37f47d 100644
--- a/src/completion/sys_tasks.rs
+++ b/src/completion/sys_tasks.rs
@@ -1,109 +1,108 @@
 use tower_lsp::lsp_types::*;
 
-/// 文档：ieee1364 page 308
+/// 文档：IEEE 1364-2005 page 308
 /// author: LSTM-Kirigaya
 /// date: 2024.12.03
 
-/// Display and write tasks ieee1364 17.1.1
+/// Display and write tasks IEEE 1364-2005 17.1.1
 /// (&str, &str, &str): (label, snippet, description)
 pub const VLOG_DISPLAY_WRITE_TASKS: &[(&str, &str, &str)] = &[
-    ("display", "$display($1);", "打印格式化字符串到标准输出。\n```verilog\n$display(\"Hello, World!\");\n```"),
-    ("displayb", "$displayb($1);", "以二进制格式打印表达式。\n```verilog\n$displayb(data);\n```"),
-    ("displayo", "$displayo($1);", "以八进制格式打印表达式。\n```verilog\n$displayo(data);\n```"),
-    ("displayh", "$displayh($1);", "以十六进制格式打印表达式。\n```verilog\n$displayh(data);\n```"),
+    ("display", "\\$display($1);", "打印格式化字符串到标准输出。\n```verilog\n$display(\"Hello, World!\");\n```"),
+    ("displayb", "\\$displayb($1);", "以二进制格式打印表达式。\n```verilog\n$displayb(data);\n```"),
+    ("displayo", "\\$displayo($1);", "以八进制格式打印表达式。\n```verilog\n$displayo(data);\n```"),
+    ("displayh", "\\$displayh($1);", "以十六进制格式打印表达式。\n```verilog\n$displayh(data);\n```"),
 
-    ("write", "$write($1);", "类似于 $display，但不自动添加换行符。\n```verilog\n$write(\"Hello, World!\");\n```"),
-    ("writeb", "$writeb($1);", "以二进制格式打印表达式，不自动添加换行符。\n```verilog\n$writeb(data);\n```"),
-    ("writeo", "$writeo($1);", "以八进制格式打印表达式，不自动添加换行符。\n```verilog\n$writeo(data);\n```"),
-    ("writeh", "$writeh($1);", "以十六进制格式打印表达式，不自动添加换行符。\n```verilog\n$writeh(data);\n```"),
+    ("write", "\\$write($1);", "类似于 $display，但不自动添加换行符。\n```verilog\n$write(\"Hello, World!\");\n```"),
+    ("writeb", "\\$writeb($1);", "以二进制格式打印表达式，不自动添加换行符。\n```verilog\n$writeb(data);\n```"),
+    ("writeo", "\\$writeo($1);", "以八进制格式打印表达式，不自动添加换行符。\n```verilog\n$writeo(data);\n```"),
+    ("writeh", "\\$writeh($1);", "以十六进制格式打印表达式，不自动添加换行符。\n```verilog\n$writeh(data);\n```"),
 ];
 
-/// Strobed monitoring ieee1364 17.1.2
+/// Strobed monitoring IEEE 1364-2005 17.1.2
 /// (&str, &str, &str): (label, snippet, description)
 pub const VLOG_STROBED_MONITOR_TASKS: &[(&str, &str, &str)] = &[
-    ("strobe", "$strobe($1);", "在当前时间步结束时打印格式化字符串。\n```verilog\n$strobe(\"Data: %d\", data);\n```"),
-    ("strobeb", "$strobeb($1);", "在当前时间步结束时以二进制格式打印表达式。\n```verilog\n$strobeb(data);\n```"),
-    ("strobeo", "$strobeo($1);", "在当前时间步结束时以八进制格式打印表达式。\n```verilog\n$strobeo(data);\n```"),
-    ("strobeh", "$strobeh($1);", "在当前时间步结束时以十六进制格式打印表达式。\n```verilog\n$strobeh(data);\n```"),
+    ("strobe", "\\$strobe($1);", "在当前时间步结束时打印格式化字符串。\n```verilog\n$strobe(\"Data: %d\", data);\n```"),
+    ("strobeb", "\\$strobeb($1);", "在当前时间步结束时以二进制格式打印表达式。\n```verilog\n$strobeb(data);\n```"),
+    ("strobeo", "\\$strobeo($1);", "在当前时间步结束时以八进制格式打印表达式。\n```verilog\n$strobeo(data);\n```"),
+    ("strobeh", "\\$strobeh($1);", "在当前时间步结束时以十六进制格式打印表达式。\n```verilog\n$strobeh(data);\n```"),
 ];
 
-/// Continuous monitoring tasks ieee1364 17.1.3
+/// Continuous monitoring tasks IEEE 1364-2005 17.1.3
 /// (&str, &str, &str): (label, snippet, description)
 pub const VLOG_CONTINUOUS_MONITORING_TASKS: &[(&str, &str, &str)] = &[
-    ("monitor", "$monitor($1);", "监控变量并在变量变化时打印。\n```verilog\n$monitor(\"Data: %d\", data);\n```"),
-    ("monitorb", "$monitorb($1);", "监控变量并在变量变化时以二进制格式打印。\n```verilog\n$monitorb(data);\n```"),
-    ("monitoro", "$monitoro($1);", "监控变量并在变量变化时以八进制格式打印。\n```verilog\n$monitoro(data);\n```"),
-    ("monitorh", "$monitorh($1);", "监控变量并在变量变化时以十六进制格式打印。\n```verilog\n$monitorh(data);\n```"),
+    ("monitor", "\\$monitor($1);", "监控变量并在变量变化时打印。\n```verilog\n$monitor(\"Data: %d\", data);\n```"),
+    ("monitorb", "\\$monitorb($1);", "监控变量并在变量变化时以二进制格式打印。\n```verilog\n$monitorb(data);\n```"),
+    ("monitoro", "\\$monitoro($1);", "监控变量并在变量变化时以八进制格式打印。\n```verilog\n$monitoro(data);\n```"),
+    ("monitorh", "\\$monitorh($1);", "监控变量并在变量变化时以十六进制格式打印。\n```verilog\n$monitorh(data);\n```"),
     // monitoron和monitoroff与后面的dumpon和dumpoff等保持一致，不带无参括号
-    ("monitoron", "$monitoron;", "启用监控任务。\n```verilog\n$monitoron();\n```"),
-    ("monitoroff", "$monitoroff;", "关闭监控任务。\n```verilog\n$monitoroff();\n```"),
+    ("monitoron", "\\$monitoron;", "启用监控任务。\n```verilog\n$monitoron();\n```"),
+    ("monitoroff", "\\$monitoroff;", "关闭监控任务。\n```verilog\n$monitoroff();\n```"),
 ];
 
-/// File input-output system tasks and functions ieee1364 17.2.1
+/// File input-output system tasks and functions IEEE 1364-2005 17.2.1
 /// (&str, &str, &str): (label, snippet, description)
 pub const VLOG_FILE_IO_TASKS: &[(&str, &str, &str)] = &[
-    ("fopen", "$fopen($1, $2);", "打开文件并返回文件句柄。\n```verilog\ninteger file_handle;\n// 默认以 \"w\" 作为 flag，如果 file_handle == 0，文件打开失败，file_handle == 1，文件打开成功\nfile_handle = $fopen(\"data.bin\", \"r\");\n```\n\n其余文件描述符\n| 参数 | 描述 |\n|------|-------|\n| `r` 或 `rb` | 以只读方式打开文件 |\n| `w` 或 `wb` | 截断文件长度为零或创建新文件以进行写入 |\n| `a` 或 `ab` | 追加；在文件末尾打开以进行写入，或创建新文件以进行写入 |\n| `r+`、`r+b` 或 `rb+` | 以读写方式打开文件 |\n| `w+`、`w+b` 或 `wb+` | 截断文件或创建新文件以进行读写 |\n| `a+`、`a+b` 或 `ab+` | 追加；在文件末尾打开或创建新文件以进行读写 |"),
-    ("fclose", "$fclose($1);", "关闭文件。\n```verilog\n$fclose(file_handle);\n```"),
+    ("fopen", "\\$fopen($1, $2);", "打开文件并返回文件句柄。\n```verilog\ninteger file_handle;\n// 默认以 \"w\" 作为 flag，如果 file_handle == 0，文件打开失败，file_handle == 1，文件打开成功\nfile_handle = $fopen(\"data.bin\", \"r\");\n```\n\n其余文件描述符\n| 参数 | 描述 |\n|------|-------|\n| `r` 或 `rb` | 以只读方式打开文件 |\n| `w` 或 `wb` | 截断文件长度为零或创建新文件以进行写入 |\n| `a` 或 `ab` | 追加；在文件末尾打开以进行写入，或创建新文件以进行写入 |\n| `r+`、`r+b` 或 `rb+` | 以读写方式打开文件 |\n| `w+`、`w+b` 或 `wb+` | 截断文件或创建新文件以进行读写 |\n| `a+`、`a+b` 或 `ab+` | 追加；在文件末尾打开或创建新文件以进行读写 |"),
+    ("fclose", "\\$fclose($1);", "关闭文件。\n```verilog\n$fclose(file_handle);\n```"),
 ];
 
-/// File output system tasks ieee1364 17.2.2
+/// File output system tasks IEEE 1364-2005 17.2.2
 /// (&str, &str, &str): (label, snippet, description)
 pub const VLOG_FILE_OUTPUT_TASKS: &[(&str, &str, &str)] = &[
-    ("fdisplay", "$fdisplay($1, $2);", "将格式化字符串写入文件。\n```verilog\n$fdisplay(file_handle, \"Data: %d\", data);\n```"),
-    ("fdisplayb", "$fdisplayb($1, $2);", "将二进制格式的表达式写入文件。\n```verilog\n$fdisplayb(file_handle, data);\n```"),
-    ("fdisplayo", "$fdisplayo($1, $2);", "将八进制格式的表达式写入文件。\n```verilog\n$fdisplayo(file_handle, data);\n```"),
-    ("fdisplayh", "$fdisplayh($1, $2);", "将十六进制格式的表达式写入文件。\n```verilog\n$fdisplayh(file_handle, data);\n```"),
+    ("fdisplay", "\\$fdisplay($1, $2);", "将格式化字符串写入文件。\n```verilog\n$fdisplay(file_handle, \"Data: %d\", data);\n```"),
+    ("fdisplayb", "\\$fdisplayb($1, $2);", "将二进制格式的表达式写入文件。\n```verilog\n$fdisplayb(file_handle, data);\n```"),
+    ("fdisplayo", "\\$fdisplayo($1, $2);", "将八进制格式的表达式写入文件。\n```verilog\n$fdisplayo(file_handle, data);\n```"),
+    ("fdisplayh", "\\$fdisplayh($1, $2);", "将十六进制格式的表达式写入文件。\n```verilog\n$fdisplayh(file_handle, data);\n```"),
 
-    ("fwrite", "$fwrite($1, $2);", "将格式化字符串写入文件，不自动添加换行符。\n```verilog\n$fwrite(file_handle, \"Data: %d\", data);\n```"),    
-    ("fwriteb", "$fwriteb($1, $2);", "将二进制格式的表达式写入文件，不自动添加换行符。\n```verilog\n$fwriteb(file_handle, data);\n```"),
-    ("fwriteo", "$fwriteo($1, $2);", "将八进制格式的表达式写入文件，不自动添加换行符。\n```verilog\n$fwriteo(file_handle, data);\n```"),
-    ("fwriteh", "$fwriteh($1, $2);", "将十六进制格式的表达式写入文件，不自动添加换行符。\n```verilog\n$fwriteh(file_handle, data);\n```"),
+    ("fwrite", "\\$fwrite($1, $2);", "将格式化字符串写入文件，不自动添加换行符。\n```verilog\n$fwrite(file_handle, \"Data: %d\", data);\n```"),    
+    ("fwriteb", "\\$fwriteb($1, $2);", "将二进制格式的表达式写入文件，不自动添加换行符。\n```verilog\n$fwriteb(file_handle, data);\n```"),
+    ("fwriteo", "\\$fwriteo($1, $2);", "将八进制格式的表达式写入文件，不自动添加换行符。\n```verilog\n$fwriteo(file_handle, data);\n```"),
+    ("fwriteh", "\\$fwriteh($1, $2);", "将十六进制格式的表达式写入文件，不自动添加换行符。\n```verilog\n$fwriteh(file_handle, data);\n```"),
 
-    ("fstrobe", "$fstrobe($1, $2);", "在当前时间步结束时将格式化字符串写入文件。\n```verilog\n$fstrobe(file_handle, \"Data: %d\", data);\n```"),    
-    ("fstrobeb", "$fstrobeb($1, $2);", "在当前时间步结束时将二进制格式的表达式写入文件。\n```verilog\n$fstrobeb(file_handle, data);\n```"),
-    ("fstrobeo", "$fstrobeo($1, $2);", "在当前时间步结束时将八进制格式的表达式写入文件。\n```verilog\n$fstrobeo(file_handle, data);\n```"),
-    ("fstrobeh", "$fstrobeh($1, $2);", "在当前时间步结束时将十六进制格式的表达式写入文件。\n```verilog\n$fstrobeh(file_handle, data);\n```"),
+    ("fstrobe", "\\$fstrobe($1, $2);", "在当前时间步结束时将格式化字符串写入文件。\n```verilog\n$fstrobe(file_handle, \"Data: %d\", data);\n```"),    
+    ("fstrobeb", "\\$fstrobeb($1, $2);", "在当前时间步结束时将二进制格式的表达式写入文件。\n```verilog\n$fstrobeb(file_handle, data);\n```"),
+    ("fstrobeo", "\\$fstrobeo($1, $2);", "在当前时间步结束时将八进制格式的表达式写入文件。\n```verilog\n$fstrobeo(file_handle, data);\n```"),
+    ("fstrobeh", "\\$fstrobeh($1, $2);", "在当前时间步结束时将十六进制格式的表达式写入文件。\n```verilog\n$fstrobeh(file_handle, data);\n```"),
 
-    ("fmonitor", "$fmonitor($1, $2);", "监控变量并在变量变化时写入文件。\n```verilog\n$fmonitor(file_handle, \"Data: %d\", data);\n```"),
-    ("fmonitorb", "$fmonitorb($1, $2);", "监控变量并在变量变化时将二进制格式的表达式写入文件。\n```verilog\n$fmonitorb(file_handle, data);\n```"),
-    ("fmonitoro", "$fmonitoro($1, $2);", "监控变量并在变量变化时将八进制格式的表达式写入文件。\n```verilog\n$fmonitoro(file_handle, data);\n```"),
-    ("fmonitorh", "$fmonitorh($1, $2);", "监控变量并在变量变化时将十六进制格式的表达式写入文件。\n```verilog\n$fmonitorh(file_handle, data);\n```"),
+    ("fmonitor", "\\$fmonitor($1, $2);", "监控变量并在变量变化时写入文件。\n```verilog\n$fmonitor(file_handle, \"Data: %d\", data);\n```"),
+    ("fmonitorb", "\\$fmonitorb($1, $2);", "监控变量并在变量变化时将二进制格式的表达式写入文件。\n```verilog\n$fmonitorb(file_handle, data);\n```"),
+    ("fmonitoro", "\\$fmonitoro($1, $2);", "监控变量并在变量变化时将八进制格式的表达式写入文件。\n```verilog\n$fmonitoro(file_handle, data);\n```"),
+    ("fmonitorh", "\\$fmonitorh($1, $2);", "监控变量并在变量变化时将十六进制格式的表达式写入文件。\n```verilog\n$fmonitorh(file_handle, data);\n```"),
 ];
 
 
-/// Formatting data to a string tasks ieee1364 17.2.3
+/// Formatting data to a string tasks IEEE 1364-2005 17.2.3
 /// (&str, &str, &str): (label, snippet, description)
 pub const VLOG_FORMATTING_TASKS: &[(&str, &str, &str)] = &[
-    ("swrite", "$swrite($1, $2);", "将格式化字符串存储到字符串变量中，不自动添加换行符。\n```verilog\nstring formatted_string;\n$swrite(formatted_string, \"Data: %d\", data);\n```"),
-    ("swriteb", "$swriteb($1, $2);", "将二进制格式的表达式存储到字符串变量中，不自动添加换行符。\n```verilog\nstring formatted_string;\n$swriteb(formatted_string, data);\n```"),
-    ("swriteo", "$swriteo($1, $2);", "将八进制格式的表达式存储到字符串变量中，不自动添加换行符。\n```verilog\nstring formatted_string;\n$swriteo(formatted_string, data);\n```"),
-    ("swriteh", "$swriteh($1, $2);", "将十六进制格式的表达式存储到字符串变量中，不自动添加换行符。\n```verilog\nstring formatted_string;\n$swriteh(formatted_string, data);\n```"),
-    ("sformat", "$sformat($1, $2);", "将格式化字符串存储到字符串变量中。\n```verilog\nstring formatted_string;\n$sformat(formatted_string, \"Data: %d\", data);\n```"),
+    ("swrite", "\\$swrite($1, $2);", "将格式化字符串存储到字符串变量中，不自动添加换行符。\n```verilog\nstring formatted_string;\n$swrite(formatted_string, \"Data: %d\", data);\n```"),
+    ("swriteb", "\\$swriteb($1, $2);", "将二进制格式的表达式存储到字符串变量中，不自动添加换行符。\n```verilog\nstring formatted_string;\n$swriteb(formatted_string, data);\n```"),
+    ("swriteo", "\\$swriteo($1, $2);", "将八进制格式的表达式存储到字符串变量中，不自动添加换行符。\n```verilog\nstring formatted_string;\n$swriteo(formatted_string, data);\n```"),
+    ("swriteh", "\\$swriteh($1, $2);", "将十六进制格式的表达式存储到字符串变量中，不自动添加换行符。\n```verilog\nstring formatted_string;\n$swriteh(formatted_string, data);\n```"),
+    ("sformat", "\\$sformat($1, $2);", "将格式化字符串存储到字符串变量中。\n```verilog\nstring formatted_string;\n$sformat(formatted_string, \"Data: %d\", data);\n```"),
 ];
 
-/// Reading data from a file tasks ieee1364 17.2.4
+/// Reading data from a file tasks IEEE 1364-2005 17.2.4
 /// (&str, &str, &str): (label, snippet, description)
 pub const VLOG_FILE_READING_TASKS: &[(&str, &str, &str)] = &[
     // 17.2.4.1 Reading a character at a time
-    ("fgetc", "$fgetc($1);", "从文件中读取一个字符。\n```verilog\ninteger char;\nchar = $fgetc(file_handle);\n```"),
-    ("ungetc", "$ungetc($1, $2);", "将字符推回到文件流中。\n```verilog\n$ungetc(char, file_handle);\n```"),
+    ("fgetc", "\\$fgetc($1);", "从文件中读取一个字符。\n```verilog\ninteger char;\nchar = $fgetc(file_handle);\n```"),
+    ("ungetc", "\\$ungetc($1, $2);", "将字符推回到文件流中。\n```verilog\n$ungetc(char, file_handle);\n```"),
 
     // 17.2.4.2 Reading a line at a time、
     // 只有两个参数 char_num = $fgets(fbuf,fd);
-    ("fgets", "$fgets($1, $2);", "从文件中读取一行数据。\n```verilog\nstring line;\n$fgets(line, file_handle);\n```"),
+    ("fgets", "\\$fgets($1, $2);", "从文件中读取一行数据。\n```verilog\nstring line;\n$fgets(line, file_handle);\n```"),
     
     // 17.2.4.3 Reading formatted data
-    ("fscanf", "$fscanf($1, $2, $3);", "从文件中读取格式化数据。\n```verilog\ninteger value;\n$fscanf(file_handle, \"%d\", value);\n```"),
-    ("sscanf", "$sscanf($1, $2, $3);", "从字符串中读取格式化数据。\n```verilog\ninteger value;\n$sscanf(\"123\", \"%d\", value);\n```"),
+    ("fscanf", "\\$fscanf($1, $2, $3);", "从文件中读取格式化数据。\n```verilog\ninteger value;\n$fscanf(file_handle, \"%d\", value);\n```"),
+    ("sscanf", "\\$sscanf($1, $2, $3);", "从字符串中读取格式化数据。\n```verilog\ninteger value;\n$sscanf(\"123\", \"%d\", value);\n```"),
 
     // 17.2.4.4 Reading binary data
-    // 漏了一个
     // integer <integer>;
     // <integer> = $fread(<store>，<file_desc>); 
     // <integer> = $fread(<store>，<file_desc>, <start> ); 
     // <integer> = $fread(<store>，<file_desc>, <start>, <count> ); 
     // <integer> = $fread(<store>，<file_desc>, , <count> ); 
-    // integer：整型数值，返回本次$fread 读取的真实字节数量，当返回值为0 ，表示错误读取或者文件结束。
+    // integer：整型数值，返回本次 $fread 读取的真实字节数量，当返回值为0 ，表示错误读取或者文件结束。
     // store：将二进制文件中的数据读取到寄存器或者二维数组中。
     // file_desc：为打开的文件句柄
     // start: 为二维数组的起始地址
@@ -111,266 +110,267 @@ pub const VLOG_FILE_READING_TASKS: &[(&str, &str, &str)] = &[
     // fread
     // integer fd;
     // reg [7:0] fbuf [3:0];
-    // char_num = $fread(fbuf, fd, 0, 4); //读取二进制文件中的数据，存放到fbuf[0],fbuf[1],fbuf[2],fbuf[3]
-    // char_num = $fread(fbuf, fd, 1, 2); //读取二进制文件中的数据，存放到fbuf[1],fbuf[2]
+    // char_num = $fread(fbuf, fd, 0, 4); // 读取二进制文件中的数据，存放到fbuf[0],fbuf[1],fbuf[2],fbuf[3]
+    // char_num = $fread(fbuf, fd, 1, 2); // 读取二进制文件中的数据，存放到fbuf[1],fbuf[2]
+    ("fread", "\\$fread($1, $2, $3, $4);", "读取二进制文件中的数据。\n```verilog\ninteger fd;\nreg [7:0] fbuf [3:0];\nchar_num = $fread(fbuf, fd, 0, 4); // 读取二进制文件中的数据，存放到fbuf[0],fbuf[1],fbuf[2],fbuf[3]\nchar_num = $fread(fbuf, fd, 1, 2); // 读取二进制文件中的数据，存放到fbuf[1],fbuf[2]\n```"),
 ];
 
-/// File positioning tasks ieee1364 17.2.5
+/// File positioning tasks IEEE 1364-2005 17.2.5
 /// (&str, &str, &str): (label, snippet, description)
 pub const VLOG_FILE_POSITIONING_TASKS: &[(&str, &str, &str)] = &[
-    ("fseek", "$fseek($1, $2, $3);", "设置文件指针位置。\n```verilog\n$fseek(file_handle, 0, 0);\n```"),
-    ("ftell", "$ftell($1);", "返回文件指针的当前位置。\n```verilog\ninteger position;\nposition = $ftell(file_handle);\n```"),
-    ("rewind", "$rewind($1);", "将文件指针重置到文件开头。\n```verilog\n$rewind(file_handle);\n```"),
+    ("fseek", "\\$fseek($1, $2, $3);", "设置文件指针位置。\n```verilog\n$fseek(file_handle, 0, 0);\n```"),
+    ("ftell", "\\$ftell($1);", "返回文件指针的当前位置。\n```verilog\ninteger position;\nposition = $ftell(file_handle);\n```"),
+    ("rewind", "\\$rewind($1);", "将文件指针重置到文件开头。\n```verilog\n$rewind(file_handle);\n```"),
 ];
 
-/// Flushing output tasks ieee1364 17.2.6
+/// Flushing output tasks IEEE 1364-2005 17.2.6
 /// (&str, &str, &str): (label, snippet, description)
 pub const VLOG_FLUSHING_OUTPUT_TASKS: &[(&str, &str, &str)] = &[
-    ("fflush", "$fflush($1);", "刷新文件缓冲区。\n```verilog\n$fflush(file_handle);\n```"),
+    ("fflush", "\\$fflush($1);", "刷新文件缓冲区。\n```verilog\n$fflush(file_handle);\n```"),
 ];
 
-/// I/O error status tasks ieee1364 17.2.7
+/// I/O error status tasks IEEE 1364-2005 17.2.7
 /// (&str, &str, &str): (label, snippet, description)
 pub const VLOG_IO_ERROR_STATUS_TASKS: &[(&str, &str, &str)] = &[
     // err = $ferror(fd, str) ; str会提供更加详细的错误信息
     // err 返回非零值表示错误, str 返回非零值存储错误类型, 官方建议 str 长度为 640bit 位宽
     // 假如打开一个不存在的文件，则err会得到00000002，str则会得到No such file or directory
-    ("ferror", "$ferror($1);", "检查文件读写错误。\n```verilog\ninteger error;\nerror = $ferror(file_handle);\n```"),
+    ("ferror", "\\$ferror($1);", "检查文件读写错误。\n```verilog\ninteger error;\nerror = $ferror(file_handle);\n```"),
 ];
 
-/// Detecting EOF tasks ieee1364 17.2.8
+/// Detecting EOF tasks IEEE 1364-2005 17.2.8
 /// (&str, &str, &str): (label, snippet, description)
 pub const VLOG_DETECTING_EOF_TASKS: &[(&str, &str, &str)] = &[
-    ("feof", "$feof($1);", "检查文件是否到达文件末尾。\n```verilog\ninteger eof;\neof = $feof(file_handle);\n```"),
+    ("feof", "\\$feof($1);", "检查文件是否到达文件末尾。\n```verilog\ninteger eof;\neof = $feof(file_handle);\n```"),
 ];
 
-/// Loading memory data from a file tasks ieee1364 17.2.9
+/// Loading memory data from a file tasks IEEE 1364-2005 17.2.9
 /// (&str, &str, &str): (label, snippet, description)
 pub const VLOG_LOADING_MEMORY_TASKS: &[(&str, &str, &str)] = &[
-    ("readmemb", "$readmemb($1, $2);", "从文件中读取二进制数据到内存。\n```verilog\n$readmemb(\"data.bin\", memory);\n```"),
-    ("readmemh", "$readmemh($1, $2);", "从文件中读取十六进制数据到内存。\n```verilog\n$readmemh(\"data.hex\", memory);\n```"),
+    ("readmemb", "\\$readmemb($1, $2);", "从文件中读取二进制数据到内存。\n```verilog\n$readmemb(\"data.bin\", memory);\n```"),
+    ("readmemh", "\\$readmemh($1, $2);", "从文件中读取十六进制数据到内存。\n```verilog\n$readmemh(\"data.hex\", memory);\n```"),
 ];
 
-/// Loading timing data from an SDF file tasks ieee1364 17.2.10
+/// Loading timing data from an SDF file tasks IEEE 1364-2005 17.2.10
 /// (&str, &str, &str): (label, snippet, description)
 pub const VLOG_LOADING_TIMING_TASKS: &[(&str, &str, &str)] = &[
     // $sdf_annotate ("sdf_file"[, module_instance][,"sdf_configfile"][,"sdf_logfile"][,"mtm_spec"][,"scale_factors"][,"scale_type"]);
     // 最简单的方式可以只需要两个参数，大概就这样就好？
     // $sdf_annotate(“ring_oscillator.sdf”,ring_oscillator);
-    ("sdf_annotate", "$sdf_annotate($1, $2);", "从 SDF 文件加载时序数据并应用于模块实例。\n```verilog\n$sdf_annotate(\"timing.sdf\", top_module);\n```"),
+    ("sdf_annotate", "\\$sdf_annotate($1, $2);", "从 SDF 文件加载时序数据并应用于模块实例。\n```verilog\n$sdf_annotate(\"timing.sdf\", top_module);\n```"),
 ];
 
-/// $printtimescale tasks ieee1364 17.3.1
+/// $printtimescale tasks IEEE 1364-2005 17.3.1
 /// (&str, &str, &str): (label, snippet, description)
 pub const VLOG_PRINTTIMESCALE_TASKS: &[(&str, &str, &str)] = &[
-    ("printtimescale", "$printtimescale($1);", "打印指定模块的时间刻度信息。\n```verilog\n$printtimescale(module_instance);\n```"),
+    ("printtimescale", "\\$printtimescale($1);", "打印指定模块的时间刻度信息。\n```verilog\n$printtimescale(module_instance);\n```"),
 ];
 
-/// $timeformat tasks ieee1364 17.3.2
+/// $timeformat tasks IEEE 1364-2005 17.3.2
 /// (&str, &str, &str): (label, snippet, description)
 pub const VLOG_TIMEFORMAT_TASKS: &[(&str, &str, &str)] = &[
-    ("timeformat", "$timeformat($1, $2, $3, $4);", "设置时间格式。\n```verilog\n$timeformat(-9, 3, \" ns\", 8);\n```"),
+    ("timeformat", "\\$timeformat($1, $2, $3, $4);", "设置时间格式。\n```verilog\n$timeformat(-9, 3, \" ns\", 8);\n```"),
 ];
 
-/// $finish tasks ieee1364 17.4.1
+/// $finish tasks IEEE 1364-2005 17.4.1
 /// (&str, &str, &str): (label, snippet, description)
 pub const VLOG_FINISH_TASKS: &[(&str, &str, &str)] = &[
-    ("finish", "$finish($1);", "终止仿真。\n```verilog\n$finish(0);\n```"),
+    ("finish", "\\$finish($1);", "终止仿真。\n```verilog\n$finish(0);\n```"),
 ];
 
-/// $stop tasks ieee1364 17.4.2
+/// $stop tasks IEEE 1364-2005 17.4.2
 /// (&str, &str, &str): (label, snippet, description)
 pub const VLOG_STOP_TASKS: &[(&str, &str, &str)] = &[
-    ("stop", "$stop($1);", "暂停仿真。\n```verilog\n$stop(0);\n```"),
+    ("stop", "\\$stop($1);", "暂停仿真。\n```verilog\n$stop(0);\n```"),
 ];
 
-/// Array types tasks ieee1364 17.5.1
+/// Array types tasks IEEE 1364-2005 17.5.1
 /// (&str, &str, &str): (label, snippet, description)
 pub const VLOG_ARRAY_TYPES_TASKS: &[(&str, &str, &str)] = &[
-    ("async$and$array", "$async$and$array($1, $2);", "对数组进行异步与操作。\n```verilog\n$async$and$array(array1, array2);\n```"),
-    ("async$nand$array", "$async$nand$array($1, $2);", "对数组进行异步与非操作。\n```verilog\n$async$nand$array(array1, array2);\n```"),
-    ("async$or$array", "$async$or$array($1, $2);", "对数组进行异步或操作。\n```verilog\n$async$or$array(array1, array2);\n```"),
-    ("async$nor$array", "$async$nor$array($1, $2);", "对数组进行异步或非操作。\n```verilog\n$async$nor$array(array1, array2);\n```"),
-    ("sync$and$array", "$sync$and$array($1, $2);", "对数组进行同步与操作。\n```verilog\n$sync$and$array(array1, array2);\n```"),
-    ("sync$nand$array", "$sync$nand$array($1, $2);", "对数组进行同步与非操作。\n```verilog\n$sync$nand$array(array1, array2);\n```"),
-    ("sync$or$array", "$sync$or$array($1, $2);", "对数组进行同步或操作。\n```verilog\n$sync$or$array(array1, array2);\n```"),
-    ("sync$nor$array", "$sync$nor$array($1, $2);", "对数组进行同步或非操作。\n```verilog\n$sync$nor$array(array1, array2);\n```"),
+    ("async$and$array", "\\$async$and$array($1, $2);", "对数组进行异步与操作。\n```verilog\n$async$and$array(array1, array2);\n```"),
+    ("async$nand$array", "\\$async$nand$array($1, $2);", "对数组进行异步与非操作。\n```verilog\n$async$nand$array(array1, array2);\n```"),
+    ("async$or$array", "\\$async$or$array($1, $2);", "对数组进行异步或操作。\n```verilog\n$async$or$array(array1, array2);\n```"),
+    ("async$nor$array", "\\$async$nor$array($1, $2);", "对数组进行异步或非操作。\n```verilog\n$async$nor$array(array1, array2);\n```"),
+    ("sync$and$array", "\\$sync$and$array($1, $2);", "对数组进行同步与操作。\n```verilog\n$sync$and$array(array1, array2);\n```"),
+    ("sync$nand$array", "\\$sync$nand$array($1, $2);", "对数组进行同步与非操作。\n```verilog\n$sync$nand$array(array1, array2);\n```"),
+    ("sync$or$array", "\\$sync$or$array($1, $2);", "对数组进行同步或操作。\n```verilog\n$sync$or$array(array1, array2);\n```"),
+    ("sync$nor$array", "\\$sync$nor$array($1, $2);", "对数组进行同步或非操作。\n```verilog\n$sync$nor$array(array1, array2);\n```"),
 ];
 
-/// Array logic types tasks ieee1364 17.5.2
+/// Array logic types tasks IEEE 1364-2005 17.5.2
 /// (&str, &str, &str): (label, snippet, description)
 pub const VLOG_ARRAY_LOGIC_TYPES_TASKS: &[(&str, &str, &str)] = &[
-    ("async$and$plane", "$async$and$plane($1, $2);", "对数组平面进行异步与操作。\n```verilog\n$async$and$plane(plane1, plane2);\n```"),
-    ("async$nand$plane", "$async$nand$plane($1, $2);", "对数组平面进行异步与非操作。\n```verilog\n$async$nand$plane(plane1, plane2);\n```"),
-    ("async$or$plane", "$async$or$plane($1, $2);", "对数组平面进行异步或操作。\n```verilog\n$async$or$plane(plane1, plane2);\n```"),
-    ("async$nor$plane", "$async$nor$plane($1, $2);", "对数组平面进行异步或非操作。\n```verilog\n$async$nor$plane(plane1, plane2);\n```"),
-    ("sync$and$plane", "$sync$and$plane($1, $2);", "对数组平面进行同步与操作。\n```verilog\n$sync$and$plane(plane1, plane2);\n```"),
-    ("sync$nand$plane", "$sync$nand$plane($1, $2);", "对数组平面进行同步与非操作。\n```verilog\n$sync$nand$plane(plane1, plane2);\n```"),
-    ("sync$or$plane", "$sync$or$plane($1, $2);", "对数组平面进行同步或操作。\n```verilog\n$sync$or$plane(plane1, plane2);\n```"),
-    ("sync$nor$plane", "$sync$nor$plane($1, $2);", "对数组平面进行同步或非操作。\n```verilog\n$sync$nor$plane(plane1, plane2);\n```"),
+    ("async$and$plane", "\\$async$and$plane($1, $2);", "对数组平面进行异步与操作。\n```verilog\n$async$and$plane(plane1, plane2);\n```"),
+    ("async$nand$plane", "\\$async$nand$plane($1, $2);", "对数组平面进行异步与非操作。\n```verilog\n$async$nand$plane(plane1, plane2);\n```"),
+    ("async$or$plane", "\\$async$or$plane($1, $2);", "对数组平面进行异步或操作。\n```verilog\n$async$or$plane(plane1, plane2);\n```"),
+    ("async$nor$plane", "\\$async$nor$plane($1, $2);", "对数组平面进行异步或非操作。\n```verilog\n$async$nor$plane(plane1, plane2);\n```"),
+    ("sync$and$plane", "\\$sync$and$plane($1, $2);", "对数组平面进行同步与操作。\n```verilog\n$sync$and$plane(plane1, plane2);\n```"),
+    ("sync$nand$plane", "\\$sync$nand$plane($1, $2);", "对数组平面进行同步与非操作。\n```verilog\n$sync$nand$plane(plane1, plane2);\n```"),
+    ("sync$or$plane", "\\$sync$or$plane($1, $2);", "对数组平面进行同步或操作。\n```verilog\n$sync$or$plane(plane1, plane2);\n```"),
+    ("sync$nor$plane", "\\$sync$nor$plane($1, $2);", "对数组平面进行同步或非操作。\n```verilog\n$sync$nor$plane(plane1, plane2);\n```"),
 ];
 
-/// $q_initialize tasks ieee1364 17.6.1
+/// $q_initialize tasks IEEE 1364-2005 17.6.1
 /// (&str, &str, &str): (label, snippet, description)
 pub const VLOG_Q_INITIALIZE_TASKS: &[(&str, &str, &str)] = &[
-    ("q_initialize", "$q_initialize($1, $2, $3, $4);", "创建新的队列。\n```verilog\n$q_initialize(q_id, q_type, max_length, status);\n```\n\nTable 17-14—队列类型表:\n\n| q_type 值 | 队列类型 |\n|-----------|----------|\n| 1         | 先进先出 |\n| 2         | 后进先出 |\n\nTable 17-16—状态代码表:\n\n| 状态代码 | 含义 |\n|----------|------|\n| 0        | 成功 |\n| 1        | 队列已满，无法添加 |\n| 2        | 未定义的 q_id |\n| 3        | 队列已空，无法移除 |\n| 4        | 不支持的队列类型，无法创建队列 |\n| 5        | 指定的长度 <= 0，无法创建队列 |\n| 6        | 重复的 q_id，无法创建队列 |\n| 7        | 内存不足，无法创建队列 |"),
+    ("q_initialize", "\\$q_initialize($1, $2, $3, $4);", "创建新的队列。\n```verilog\n$q_initialize(q_id, q_type, max_length, status);\n```\n\nTable 17-14—队列类型表:\n\n| q_type 值 | 队列类型 |\n|-----------|----------|\n| 1         | 先进先出 |\n| 2         | 后进先出 |\n\nTable 17-16—状态代码表:\n\n| 状态代码 | 含义 |\n|----------|------|\n| 0        | 成功 |\n| 1        | 队列已满，无法添加 |\n| 2        | 未定义的 q_id |\n| 3        | 队列已空，无法移除 |\n| 4        | 不支持的队列类型，无法创建队列 |\n| 5        | 指定的长度 <= 0，无法创建队列 |\n| 6        | 重复的 q_id，无法创建队列 |\n| 7        | 内存不足，无法创建队列 |"),
 ];
 
-/// $q_add tasks ieee1364 17.6.2
+/// $q_add tasks IEEE 1364-2005 17.6.2
 /// (&str, &str, &str): (label, snippet, description)
 pub const VLOG_Q_ADD_TASKS: &[(&str, &str, &str)] = &[
-    ("q_add", "$q_add($1, $2, $3, $4);", "向队列中添加一个条目。\n```verilog\n$q_add(q_id, job_id, inform_id, status);\n```\n\nTable 17-16—状态代码表:\n\n| 状态代码 | 含义 |\n|----------|------|\n| 0        | 成功 |\n| 1        | 队列已满，无法添加 |\n| 2        | 未定义的 q_id |\n| 3        | 队列已空，无法移除 |\n| 4        | 不支持的队列类型，无法创建队列 |\n| 5        | 指定的长度 <= 0，无法创建队列 |\n| 6        | 重复的 q_id，无法创建队列 |\n| 7        | 内存不足，无法创建队列 |"),
+    ("q_add", "\\$q_add($1, $2, $3, $4);", "向队列中添加一个条目。\n```verilog\n$q_add(q_id, job_id, inform_id, status);\n```\n\nTable 17-16—状态代码表:\n\n| 状态代码 | 含义 |\n|----------|------|\n| 0        | 成功 |\n| 1        | 队列已满，无法添加 |\n| 2        | 未定义的 q_id |\n| 3        | 队列已空，无法移除 |\n| 4        | 不支持的队列类型，无法创建队列 |\n| 5        | 指定的长度 <= 0，无法创建队列 |\n| 6        | 重复的 q_id，无法创建队列 |\n| 7        | 内存不足，无法创建队列 |"),
 ];
 
-/// $q_remove tasks ieee1364 17.6.3
+/// $q_remove tasks IEEE 1364-2005 17.6.3
 /// (&str, &str, &str): (label, snippet, description)
 pub const VLOG_Q_REMOVE_TASKS: &[(&str, &str, &str)] = &[
-    ("q_remove", "$q_remove($1, $2, $3, $4);", "从队列中移除一个条目。\n```verilog\n$q_remove(q_id, job_id, inform_id, status);\n```\n\nTable 17-16—状态代码表:\n\n| 状态代码 | 含义 |\n|----------|------|\n| 0        | 成功 |\n| 1        | 队列已满，无法添加 |\n| 2        | 未定义的 q_id |\n| 3        | 队列已空，无法移除 |\n| 4        | 不支持的队列类型，无法创建队列 |\n| 5        | 指定的长度 <= 0，无法创建队列 |\n| 6        | 重复的 q_id，无法创建队列 |\n| 7        | 内存不足，无法创建队列 |"),
+    ("q_remove", "\\$q_remove($1, $2, $3, $4);", "从队列中移除一个条目。\n```verilog\n$q_remove(q_id, job_id, inform_id, status);\n```\n\nTable 17-16—状态代码表:\n\n| 状态代码 | 含义 |\n|----------|------|\n| 0        | 成功 |\n| 1        | 队列已满，无法添加 |\n| 2        | 未定义的 q_id |\n| 3        | 队列已空，无法移除 |\n| 4        | 不支持的队列类型，无法创建队列 |\n| 5        | 指定的长度 <= 0，无法创建队列 |\n| 6        | 重复的 q_id，无法创建队列 |\n| 7        | 内存不足，无法创建队列 |"),
 ];
 
-/// $q_full tasks ieee1364 17.6.4
+/// $q_full tasks IEEE 1364-2005 17.6.4
 /// (&str, &str, &str): (label, snippet, description)
 pub const VLOG_Q_FULL_TASKS: &[(&str, &str, &str)] = &[
-    ("q_full", "$q_full($1, $2);", "检查队列是否有空间再添加一个条目。\n```verilog\ninteger is_full;\nis_full = $q_full(q_id, status);\n```\n\nTable 17-16—状态代码表:\n\n| 状态代码 | 含义 |\n|----------|------|\n| 0        | 成功 |\n| 1        | 队列已满，无法添加 |\n| 2        | 未定义的 q_id |\n| 3        | 队列已空，无法移除 |\n| 4        | 不支持的队列类型，无法创建队列 |\n| 5        | 指定的长度 <= 0，无法创建队列 |\n| 6        | 重复的 q_id，无法创建队列 |\n| 7        | 内存不足，无法创建队列 |"),
+    ("q_full", "\\$q_full($1, $2);", "检查队列是否有空间再添加一个条目。\n```verilog\ninteger is_full;\nis_full = $q_full(q_id, status);\n```\n\nTable 17-16—状态代码表:\n\n| 状态代码 | 含义 |\n|----------|------|\n| 0        | 成功 |\n| 1        | 队列已满，无法添加 |\n| 2        | 未定义的 q_id |\n| 3        | 队列已空，无法移除 |\n| 4        | 不支持的队列类型，无法创建队列 |\n| 5        | 指定的长度 <= 0，无法创建队列 |\n| 6        | 重复的 q_id，无法创建队列 |\n| 7        | 内存不足，无法创建队列 |"),
 ];
 
-/// $q_exam tasks ieee1364 17.6.5
+/// $q_exam tasks IEEE 1364-2005 17.6.5
 /// (&str, &str, &str): (label, snippet, description)
 pub const VLOG_Q_EXAM_TASKS: &[(&str, &str, &str)] = &[
-    ("q_exam", "$q_exam($1, $2, $3, $4);", "提供关于队列 q_id 活动的统计信息。\n```verilog\n$q_exam(q_id, q_stat_code, q_stat_value, status);\n```\n\nTable 17-15—$q_exam 系统任务的参数值:\n\n| 请求的 q_stat_code 值 | 从 q_stat_value 接收到的信息 |\n|-----------------------|------------------------------|\n| 1                     | 当前队列长度                 |\n| 2                     | 平均到达间隔时间             |\n| 3                     | 最大队列长度                 |\n| 4                     | 最短等待时间                 |\n| 5                     | 队列中作业的最长等待时间     |\n| 6                     | 队列中的平均等待时间         |\n\nTable 17-16—状态代码表:\n\n| 状态代码 | 含义 |\n|----------|------|\n| 0        | 成功 |\n| 1        | 队列已满，无法添加 |\n| 2        | 未定义的 q_id |\n| 3        | 队列已空，无法移除 |\n| 4        | 不支持的队列类型，无法创建队列 |\n| 5        | 指定的长度 <= 0，无法创建队列 |\n| 6        | 重复的 q_id，无法创建队列 |\n| 7        | 内存不足，无法创建队列 |"),
+    ("q_exam", "\\$q_exam($1, $2, $3, $4);", "提供关于队列 q_id 活动的统计信息。\n```verilog\n$q_exam(q_id, q_stat_code, q_stat_value, status);\n```\n\nTable 17-15—$q_exam 系统任务的参数值:\n\n| 请求的 q_stat_code 值 | 从 q_stat_value 接收到的信息 |\n|-----------------------|------------------------------|\n| 1                     | 当前队列长度                 |\n| 2                     | 平均到达间隔时间             |\n| 3                     | 最大队列长度                 |\n| 4                     | 最短等待时间                 |\n| 5                     | 队列中作业的最长等待时间     |\n| 6                     | 队列中的平均等待时间         |\n\nTable 17-16—状态代码表:\n\n| 状态代码 | 含义 |\n|----------|------|\n| 0        | 成功 |\n| 1        | 队列已满，无法添加 |\n| 2        | 未定义的 q_id |\n| 3        | 队列已空，无法移除 |\n| 4        | 不支持的队列类型，无法创建队列 |\n| 5        | 指定的长度 <= 0，无法创建队列 |\n| 6        | 重复的 q_id，无法创建队列 |\n| 7        | 内存不足，无法创建队列 |"),
 ];
 
-/// $time tasks ieee1364 17.7.1
+/// $time tasks IEEE 1364-2005 17.7.1
 /// (&str, &str, &str): (label, snippet, description)
 pub const VLOG_TIME_TASKS: &[(&str, &str, &str)] = &[
-    ("time", "$time;", "返回当前仿真时间。\n```verilog\ninteger current_time;\ncurrent_time = $time;\n```"),
+    ("time", "\\$time;", "返回当前仿真时间。\n```verilog\ninteger current_time;\ncurrent_time = $time;\n```"),
 ];
 
-/// $stime tasks ieee1364 17.7.2
+/// $stime tasks IEEE 1364-2005 17.7.2
 /// (&str, &str, &str): (label, snippet, description)
 pub const VLOG_STIME_TASKS: &[(&str, &str, &str)] = &[
-    ("stime", "$stime;", "返回当前仿真时间（以整数形式）。\n```verilog\ninteger current_time;\ncurrent_time = $stime;\n```"),
+    ("stime", "\\$stime;", "返回当前仿真时间（以整数形式）。\n```verilog\ninteger current_time;\ncurrent_time = $stime;\n```"),
 ];
 
-/// $realtime tasks ieee1364 17.7.3
+/// $realtime tasks IEEE 1364-2005 17.7.3
 /// (&str, &str, &str): (label, snippet, description)
 pub const VLOG_REALTIME_TASKS: &[(&str, &str, &str)] = &[
-    ("realtime", "$realtime;", "返回当前仿真时间（以实数形式）。\n```verilog\nreal current_time;\ncurrent_time = $realtime;\n```"),
+    ("realtime", "\\$realtime;", "返回当前仿真时间（以实数形式）。\n```verilog\nreal current_time;\ncurrent_time = $realtime;\n```"),
 ];
 
-/// Conversion functions tasks ieee1364 17.8
+/// Conversion functions tasks IEEE 1364-2005 17.8
 /// (&str, &str, &str): (label, snippet, description)
 pub const VLOG_CONVERSION_FUNCTIONS_TASKS: &[(&str, &str, &str)] = &[
-    ("itor", "$itor($1);", "将整数转换为实数。\n```verilog\nreal real_value;\nreal_value = $itor(integer_value);\n```"),
-    ("rtoi", "$rtoi($1);", "将实数转换为整数。\n```verilog\ninteger integer_value;\ninteger_value = $rtoi(real_value);\n```"),
-    ("bitstoreal", "$bitstoreal($1);", "将 64 位位向量转换为实数。\n```verilog\nreal real_value;\nreal_value = $bitstoreal(bit_vector);\n```"),
-    ("realtobits", "$realtobits($1);", "将实数转换为 64 位位向量。\n```verilog\nreg [63:0] bit_vector;\nbit_vector = $realtobits(real_value);\n```"),
-    // bitstoshortreal和shortrealtobits是sv中的task
-    ("bitstoshortreal", "$bitstoshortreal($1);", "将 32 位位向量转换为短实数。\n```verilog\nshortreal shortreal_value;\nshortreal_value = $bitstoshortreal(bit_vector);\n```"),
-    ("shortrealtobits", "$shortrealtobits($1);", "将短实数转换为 32 位位向量。\n```verilog\nreg [31:0] bit_vector;\nbit_vector = $shortrealtobits(shortreal_value);\n```"),
+    ("itor", "\\$itor($1);", "将整数转换为实数。\n```verilog\nreal real_value;\nreal_value = $itor(integer_value);\n```"),
+    ("rtoi", "\\$rtoi($1);", "将实数转换为整数。\n```verilog\ninteger integer_value;\ninteger_value = $rtoi(real_value);\n```"),
+    ("bitstoreal", "\\$bitstoreal($1);", "将 64 位位向量转换为实数。\n```verilog\nreal real_value;\nreal_value = $bitstoreal(bit_vector);\n```"),
+    ("realtobits", "\\$realtobits($1);", "将实数转换为 64 位位向量。\n```verilog\nreg [63:0] bit_vector;\nbit_vector = $realtobits(real_value);\n```"),
+    // bitstoshortreal 和 shortrealtobits 是 sv 中的 task
+    ("bitstoshortreal", "\\$bitstoshortreal($1);", "(system verilog) 将 32 位位向量转换为短实数。\n```verilog\nshortreal shortreal_value;\nshortreal_value = $bitstoshortreal(bit_vector);\n```"),
+    ("shortrealtobits", "\\$shortrealtobits($1);", "(system verilog) 将短实数转换为 32 位位向量。\n```verilog\nreg [31:0] bit_vector;\nbit_vector = $shortrealtobits(shortreal_value);\n```"),
 ];
 
-/// $random function tasks ieee1364 17.9.1
+/// $random function tasks IEEE 1364-2005 17.9.1
 /// (&str, &str, &str): (label, snippet, description)
 pub const VLOG_RANDOM_FUNCTION_TASKS: &[(&str, &str, &str)] = &[
-    ("random", "$random($1);", "生成一个随机数。\n```verilog\ninteger rand_num;\nrand_num = $random(seed);\n```"),
+    ("random", "\\$random($1);", "生成一个随机数。\n```verilog\ninteger rand_num;\nrand_num = $random(seed);\n```"),
 ];
 
-/// $dist_functions tasks ieee1364 17.9.2
+/// $dist_functions tasks IEEE 1364-2005 17.9.2
 /// (&str, &str, &str): (label, snippet, description)
 pub const VLOG_DIST_FUNCTIONS_TASKS: &[(&str, &str, &str)] = &[
-    ("dist_chi_square", "$dist_chi_square($1, $2);", "生成一个卡方分布的随机数。\n```verilog\nreal rand_num;\nrand_num = $dist_chi_square(seed, k);\n```"),
-    ("dist_erlang", "$dist_erlang($1, $2, $3);", "生成一个埃尔朗分布的随机数。\n```verilog\nreal rand_num;\nrand_num = $dist_erlang(seed, k, lambda);\n```"),
-    ("dist_exponential", "$dist_exponential($1, $2);", "生成一个指数分布的随机数。\n```verilog\nreal rand_num;\nrand_num = $dist_exponential(seed, lambda);\n```"),
-    ("dist_normal", "$dist_normal($1, $2, $3);", "生成一个正态分布的随机数。\n```verilog\nreal rand_num;\nrand_num = $dist_normal(seed, mean, stddev);\n```"),
-    ("dist_poisson", "$dist_poisson($1, $2);", "生成一个泊松分布的随机数。\n```verilog\nreal rand_num;\nrand_num = $dist_poisson(seed, lambda);\n```"),
-    ("dist_t", "$dist_t($1, $2);", "生成一个 t 分布的随机数。\n```verilog\nreal rand_num;\nrand_num = $dist_t(seed, v);\n```"),
-    ("dist_uniform", "$dist_uniform($1, $2, $3);", "生成一个均匀分布的随机数。\n```verilog\nreal rand_num;\nrand_num = $dist_uniform(seed, low, high);\n```"),
+    ("dist_chi_square", "\\$dist_chi_square($1, $2);", "生成一个卡方分布的随机数。\n```verilog\nreal rand_num;\nrand_num = $dist_chi_square(seed, k);\n```"),
+    ("dist_erlang", "\\$dist_erlang($1, $2, $3);", "生成一个埃尔朗分布的随机数。\n```verilog\nreal rand_num;\nrand_num = $dist_erlang(seed, k, lambda);\n```"),
+    ("dist_exponential", "\\$dist_exponential($1, $2);", "生成一个指数分布的随机数。\n```verilog\nreal rand_num;\nrand_num = $dist_exponential(seed, lambda);\n```"),
+    ("dist_normal", "\\$dist_normal($1, $2, $3);", "生成一个正态分布的随机数。\n```verilog\nreal rand_num;\nrand_num = $dist_normal(seed, mean, stddev);\n```"),
+    ("dist_poisson", "\\$dist_poisson($1, $2);", "生成一个泊松分布的随机数。\n```verilog\nreal rand_num;\nrand_num = $dist_poisson(seed, lambda);\n```"),
+    ("dist_t", "\\$dist_t($1, $2);", "生成一个 t 分布的随机数。\n```verilog\nreal rand_num;\nrand_num = $dist_t(seed, v);\n```"),
+    ("dist_uniform", "\\$dist_uniform($1, $2, $3);", "生成一个均匀分布的随机数。\n```verilog\nreal rand_num;\nrand_num = $dist_uniform(seed, low, high);\n```"),
 ];
 
-/// $test$plusargs (string) tasks ieee1364 17.10.1
+/// $test$plusargs (string) tasks IEEE 1364-2005 17.10.1
 /// (&str, &str, &str): (label, snippet, description)
 pub const VLOG_TEST_PLUSARGS_TASKS: &[(&str, &str, &str)] = &[
-    ("test$plusargs", "$test$plusargs($1);", "检查仿真命令行参数中是否包含指定的字符串。\n```verilog\ninteger result;\nresult = $test$plusargs(\"test_string\");\n```\n\n示例代码：\n```verilog\ninitial begin\n\tif ($test$plusargs(\"HELLO\")) $display(\"Hello argument found.\");\n\tif ($test$plusargs(\"HE\")) $display(\"The HE subset string is detected.\");\n\tif ($test$plusargs(\"H\")) $display(\"Argument starting with H found.\");\n\tif ($test$plusargs(\"HELLO_HERE\")) $display(\"Long argument.\");\n\tif ($test$plusargs(\"HI\")) $display(\"Simple greeting.\");\n\tif ($test$plusargs(\"LO\")) $display(\"Does not match.\");\nend\n```"),
+    ("test$plusargs", "\\$test$plusargs($1);", "检查仿真命令行参数中是否包含指定的字符串。\n```verilog\ninteger result;\nresult = $test$plusargs(\"test_string\");\n```\n\n示例代码：\n```verilog\ninitial begin\n\tif ($test$plusargs(\"HELLO\")) $display(\"Hello argument found.\");\n\tif ($test$plusargs(\"HE\")) $display(\"The HE subset string is detected.\");\n\tif ($test$plusargs(\"H\")) $display(\"Argument starting with H found.\");\n\tif ($test$plusargs(\"HELLO_HERE\")) $display(\"Long argument.\");\n\tif ($test$plusargs(\"HI\")) $display(\"Simple greeting.\");\n\tif ($test$plusargs(\"LO\")) $display(\"Does not match.\");\nend\n```"),
 ];
 
-/// $value$plusargs (user_string, variable) tasks ieee1364 17.10.2
+/// $value$plusargs (user_string, variable) tasks IEEE 1364-2005 17.10.2
 /// (&str, &str, &str): (label, snippet, description)
 pub const VLOG_VALUE_PLUSARGS_TASKS: &[(&str, &str, &str)] = &[
-    ("value$plusargs", "$value$plusargs($1, $2);", "从仿真命令行参数中提取值并赋给变量。\n```verilog\ninteger result;\nresult = $value$plusargs(\"test_string=\", value);\n```\n\n示例代码：\n```verilog\n`define STRING reg [1024 * 8:1]\nmodule goodtasks;\n\t`STRING str;\n\tinteger int;\n\treg [31:0] vect;\n\treal realvar;\n\tinitial\n\tbegin\n\t\tif ($value$plusargs(\"TEST=%d\", int))\n\t\t\t$display(\"value was %d\", int);\n\t\telse\n\t\t\t$display(\"+TEST= not found\");\n\t\t#100 $finish;\n\tend\nendmodule\n```"),
+    ("value$plusargs", "\\$value$plusargs($1, $2);", "从仿真命令行参数中提取值并赋给变量。\n```verilog\ninteger result;\nresult = $value$plusargs(\"test_string=\", value);\n```\n\n示例代码：\n```verilog\n`define STRING reg [1024 * 8:1]\nmodule goodtasks;\n\t`STRING str;\n\tinteger int;\n\treg [31:0] vect;\n\treal realvar;\n\tinitial\n\tbegin\n\t\tif ($value$plusargs(\"TEST=%d\", int))\n\t\t\t$display(\"value was %d\", int);\n\t\telse\n\t\t\t$display(\"+TEST= not found\");\n\t\t#100 $finish;\n\tend\nendmodule\n```"),
 ];
 
-/// Integer math functions tasks ieee1364 17.11.1
+/// Integer math functions tasks IEEE 1364-2005 17.11.1
 /// (&str, &str, &str): (label, snippet, description)
 pub const VLOG_INTEGER_MATH_FUNCTIONS_TASKS: &[(&str, &str, &str)] = &[
-    ("clog2", "$clog2($1);", "返回大于或等于给定整数的最小 2 的幂次。\n```verilog\ninteger result;\nresult = $clog2(value);\n```"),
-    ("countones", "$countones($1);", "返回位向量中 1 的个数。\n```verilog\ninteger count;\ncount = $countones(bit_vector);\n```"),
-    ("isunknown", "$isunknown($1);", "检查位向量中是否有未知值（x 或 z）。\n```verilog\ninteger result;\nresult = $isunknown(bit_vector);\n```"),
-    ("onehot", "$onehot($1);", "检查位向量中是否只有一个位为 1。\n```verilog\ninteger result;\nresult = $onehot(bit_vector);\n```"),
-    ("onehot0", "$onehot0($1);", "检查位向量中是否只有一个位为 1 或没有位为 1。\n```verilog\ninteger result;\nresult = $onehot0(bit_vector);\n```"),
+    ("clog2", "\\$clog2($1);", "返回大于或等于给定整数的最小 2 的幂次。\n```verilog\ninteger result;\nresult = $clog2(value);\n```"),
+    ("countones", "\\$countones($1);", "返回位向量中 1 的个数。\n```verilog\ninteger count;\ncount = $countones(bit_vector);\n```"),
+    ("isunknown", "\\$isunknown($1);", "检查位向量中是否有未知值（x 或 z）。\n```verilog\ninteger result;\nresult = $isunknown(bit_vector);\n```"),
+    ("onehot", "\\$onehot($1);", "检查位向量中是否只有一个位为 1。\n```verilog\ninteger result;\nresult = $onehot(bit_vector);\n```"),
+    ("onehot0", "\\$onehot0($1);", "检查位向量中是否只有一个位为 1 或没有位为 1。\n```verilog\ninteger result;\nresult = $onehot0(bit_vector);\n```"),
 ];
 
-/// Real math functions tasks ieee1364 17.11.2
+/// Real math functions tasks IEEE 1364-2005 17.11.2
 /// (&str, &str, &str): (label, snippet, description)
 pub const VLOG_REAL_MATH_FUNCTIONS_TASKS: &[(&str, &str, &str)] = &[
-    ("ln", "$ln($1);", "计算自然对数。\n```verilog\nreal result;\nresult = $ln(value);\n```"),
-    ("log10", "$log10($1);", "计算以 10 为底的对数。\n```verilog\nreal result;\nresult = $log10(value);\n```"),
-    ("exp", "$exp($1);", "计算指数函数。\n```verilog\nreal result;\nresult = $exp(value);\n```"),
-    ("sqrt", "$sqrt($1);", "计算平方根。\n```verilog\nreal result;\nresult = $sqrt(value);\n```"),
-    ("pow", "$pow($1, $2);", "计算幂函数。\n```verilog\nreal result;\nresult = $pow(base, exponent);\n```"),
-    ("floor", "$floor($1);", "返回不大于给定实数的最大整数。\n```verilog\nreal result;\nresult = $floor(value);\n```"),
-    ("ceil", "$ceil($1);", "返回不小于给定实数的最小整数。\n```verilog\nreal result;\nresult = $ceil(value);\n```"),
-    ("sin", "$sin($1);", "计算正弦函数。\n```verilog\nreal result;\nresult = $sin(value);\n```"),
-    ("cos", "$cos($1);", "计算余弦函数。\n```verilog\nreal result;\nresult = $cos(value);\n```"),
-    ("tan", "$tan($1);", "计算正切函数。\n```verilog\nreal result;\nresult = $tan(value);\n```"),
-    ("asin", "$asin($1);", "计算反正弦函数。\n```verilog\nreal result;\nresult = $asin(value);\n```"),
-    ("acos", "$acos($1);", "计算反余弦函数。\n```verilog\nreal result;\nresult = $acos(value);\n```"),
-    ("atan", "$atan($1);", "计算反正切函数。\n```verilog\nreal result;\nresult = $atan(value);\n```"),
-    ("atan2", "$atan2($1, $2);", "计算反正切函数（带两个参数）。\n```verilog\nreal result;\nresult = $atan2(y, x);\n```"),
-    ("hypot", "$hypot($1, $2);", "计算直角三角形的斜边长度。\n```verilog\nreal result;\nresult = $hypot(x, y);\n```"),
-    ("sinh", "$sinh($1);", "计算双曲正弦函数。\n```verilog\nreal result;\nresult = $sinh(value);\n```"),
-    ("cosh", "$cosh($1);", "计算双曲余弦函数。\n```verilog\nreal result;\nresult = $cosh(value);\n```"),
-    ("tanh", "$tanh($1);", "计算双曲正切函数。\n```verilog\nreal result;\nresult = $tanh(value);\n```"),
-    ("asinh", "$asinh($1);", "计算反双曲正弦函数。\n```verilog\nreal result;\nresult = $asinh(value);\n```"),
-    ("acosh", "$acosh($1);", "计算反双曲余弦函数。\n```verilog\nreal result;\nresult = $acosh(value);\n```"),
-    ("atanh", "$atanh($1);", "计算反双曲正切函数。\n```verilog\nreal result;\nresult = $atanh(value);\n```"),
+    ("ln", "\\$ln($1);", "计算自然对数。\n```verilog\nreal result;\nresult = $ln(value);\n```"),
+    ("log10", "\\$log10($1);", "计算以 10 为底的对数。\n```verilog\nreal result;\nresult = $log10(value);\n```"),
+    ("exp", "\\$exp($1);", "计算指数函数。\n```verilog\nreal result;\nresult = $exp(value);\n```"),
+    ("sqrt", "\\$sqrt($1);", "计算平方根。\n```verilog\nreal result;\nresult = $sqrt(value);\n```"),
+    ("pow", "\\$pow($1, $2);", "计算幂函数。\n```verilog\nreal result;\nresult = $pow(base, exponent);\n```"),
+    ("floor", "\\$floor($1);", "返回不大于给定实数的最大整数。\n```verilog\nreal result;\nresult = $floor(value);\n```"),
+    ("ceil", "\\$ceil($1);", "返回不小于给定实数的最小整数。\n```verilog\nreal result;\nresult = $ceil(value);\n```"),
+    ("sin", "\\$sin($1);", "计算正弦函数。\n```verilog\nreal result;\nresult = $sin(value);\n```"),
+    ("cos", "\\$cos($1);", "计算余弦函数。\n```verilog\nreal result;\nresult = $cos(value);\n```"),
+    ("tan", "\\$tan($1);", "计算正切函数。\n```verilog\nreal result;\nresult = $tan(value);\n```"),
+    ("asin", "\\$asin($1);", "计算反正弦函数。\n```verilog\nreal result;\nresult = $asin(value);\n```"),
+    ("acos", "\\$acos($1);", "计算反余弦函数。\n```verilog\nreal result;\nresult = $acos(value);\n```"),
+    ("atan", "\\$atan($1);", "计算反正切函数。\n```verilog\nreal result;\nresult = $atan(value);\n```"),
+    ("atan2", "\\$atan2($1, $2);", "计算反正切函数（带两个参数）。\n```verilog\nreal result;\nresult = $atan2(y, x);\n```"),
+    ("hypot", "\\$hypot($1, $2);", "计算直角三角形的斜边长度。\n```verilog\nreal result;\nresult = $hypot(x, y);\n```"),
+    ("sinh", "\\$sinh($1);", "计算双曲正弦函数。\n```verilog\nreal result;\nresult = $sinh(value);\n```"),
+    ("cosh", "\\$cosh($1);", "计算双曲余弦函数。\n```verilog\nreal result;\nresult = $cosh(value);\n```"),
+    ("tanh", "\\$tanh($1);", "计算双曲正切函数。\n```verilog\nreal result;\nresult = $tanh(value);\n```"),
+    ("asinh", "\\$asinh($1);", "计算反双曲正弦函数。\n```verilog\nreal result;\nresult = $asinh(value);\n```"),
+    ("acosh", "\\$acosh($1);", "计算反双曲余弦函数。\n```verilog\nreal result;\nresult = $acosh(value);\n```"),
+    ("atanh", "\\$atanh($1);", "计算反双曲正切函数。\n```verilog\nreal result;\nresult = $atanh(value);\n```"),
 ];
 
-/// Specifying name of dump file ($dumpfile) tasks ieee1364 18.1.1
+/// Specifying name of dump file ($dumpfile) tasks IEEE 1364-2005 18.1.1
 /// (&str, &str, &str): (label, snippet, description)
 pub const VLOG_DUMPFILE_TASKS: &[(&str, &str, &str)] = &[
-    ("dumpfile", "$dumpfile($1);", "指定波形转储文件的名称。\n```verilog\n$dumpfile(\"waveform.vcd\");\n```"),
+    ("dumpfile", "\\$dumpfile($1);", "指定波形转储文件的名称。\n```verilog\n$dumpfile(\"waveform.vcd\");\n```"),
 ];
 
-/// Specifying variables to be dumped ($dumpvars) tasks ieee1364 18.1.2
+/// Specifying variables to be dumped ($dumpvars) tasks IEEE 1364-2005 18.1.2
 /// (&str, &str, &str): (label, snippet, description)
 pub const VLOG_DUMPVARS_TASKS: &[(&str, &str, &str)] = &[
-    ("dumpvars", "$dumpvars($1, $2);", "指定要转储的变量。\n```verilog\n$dumpvars(1, module_instance);\n```"),
+    ("dumpvars", "\\$dumpvars($1, $2);", "指定要转储的变量。\n```verilog\n$dumpvars(1, module_instance);\n```"),
 ];
 
-/// Stopping and resuming the dump ($dumpoff/$dumpon) tasks ieee1364 18.1.3
+/// Stopping and resuming the dump ($dumpoff/$dumpon) tasks IEEE 1364-2005 18.1.3
 /// (&str, &str, &str): (label, snippet, description)
 pub const VLOG_DUMPOFF_DUMPON_TASKS: &[(&str, &str, &str)] = &[
-    ("dumpoff", "$dumpoff;", "暂停波形转储。\n```verilog\n$dumpoff;\n```"),
-    ("dumpon", "$dumpon;", "恢复波形转储。\n```verilog\n$dumpon;\n```"),
+    ("dumpoff", "\\$dumpoff;", "暂停波形转储。\n```verilog\n$dumpoff;\n```"),
+    ("dumpon", "\\$dumpon;", "恢复波形转储。\n```verilog\n$dumpon;\n```"),
 ];
 
-/// Generating a checkpoint ($dumpall) tasks ieee1364 18.1.4
+/// Generating a checkpoint ($dumpall) tasks IEEE 1364-2005 18.1.4
 /// (&str, &str, &str): (label, snippet, description)
 pub const VLOG_DUMPALL_TASKS: &[(&str, &str, &str)] = &[
-    ("dumpall", "$dumpall;", "生成一个检查点，转储所有变量的当前状态。\n```verilog\n$dumpall;\n```"),
+    ("dumpall", "\\$dumpall;", "生成一个检查点，转储所有变量的当前状态。\n```verilog\n$dumpall;\n```"),
 ];
 
-/// Limiting size of dump file ($dumplimit) tasks ieee1364 18.1.5
+/// Limiting size of dump file ($dumplimit) tasks IEEE 1364-2005 18.1.5
 /// (&str, &str, &str): (label, snippet, description)
 pub const VLOG_DUMPLIMIT_TASKS: &[(&str, &str, &str)] = &[
-    ("dumplimit", "$dumplimit($1);", "限制波形转储文件的大小。\n```verilog\n$dumplimit(1000000);\n```"),
+    ("dumplimit", "\\$dumplimit($1);", "限制波形转储文件的大小。\n```verilog\n$dumplimit(1000000);\n```"),
 ];
 
-/// Reading dump file during simulation ($dumpflush) tasks ieee1364 18.1.6
+/// Reading dump file during simulation ($dumpflush) tasks IEEE 1364-2005 18.1.6
 /// (&str, &str, &str): (label, snippet, description)
 pub const VLOG_DUMPFLUSH_TASKS: &[(&str, &str, &str)] = &[
-    ("dumpflush", "$dumpflush;", "刷新波形转储文件，确保所有数据都写入文件。\n```verilog\n$dumpflush;\n```"),
+    ("dumpflush", "\\$dumpflush;", "刷新波形转储文件，确保所有数据都写入文件。\n```verilog\n$dumpflush;\n```"),
 ];
 
 // 18.3 Creating extended VCD File
@@ -383,14 +383,51 @@ pub const VLOG_DUMPFLUSH_TASKS: &[(&str, &str, &str)] = &[
 // vcdclose         $vcdclose
 // vcdclose的信息比较少，文档中的sample是$vcdclose #13000 $end，vcdclose_task ::= $vcdclose final_simulation_time $end，感觉应该是要和$end连用的
 
+/// Specifying dump file name and ports to be dumped ($dumpports) tasks IEEE 1364-2005 18.3.1
+/// (&str, &str, &str): (label, snippet, description)
+pub const VLOG_DUMPPORTS_TASKS: &[(&str, &str, &str)] = &[
+    ("dumpports", "\\$dumpports($1, $2);", "`$dumpports` 任务用于指定 VCD 文件的名称以及要转储的端口。\n```verilog\n$dumpports(top_module, \"waveform.vcd\");\n$dumpports(module_A, module_B, module_C, \"waveform.vcd\");\n```"),
+];
+
+/// Stopping and resuming the dump ($dumpportsoff/$dumpportson) tasks IEEE 1364-2005 18.3.2
+/// (&str, &str, &str): (label, snippet, description)
+pub const VLOG_DUMPPORTSOFF_DUMPPORTSON_TASKS: &[(&str, &str, &str)] = &[
+    ("dumpportsoff", "\\$dumpportsoff($1);", "暂停端口波形转储。\n```verilog\n$dumpportsoff(\"waveform.vcd\");\n```"),
+    ("dumpportson", "\\$dumpportson($1);", "恢复端口波形转储。\n```verilog\n$dumpportson(\"waveform.vcd\");\n```"),
+];
+
+/// Generating a checkpoint ($dumpportsall) tasks IEEE 1364-2005 18.3.3
+/// (&str, &str, &str): (label, snippet, description)
+pub const VLOG_DUMPPORTSALL_TASKS: &[(&str, &str, &str)] = &[
+    ("dumpportsall", "\\$dumpportsall($1);", "`$dumpportsall` 系统任务在 VCD 文件中创建一个检查点，显示仿真中该时刻所有选定端口的值，无论自上次时间步以来端口值是否发生变化。\n```verilog\n$dumpportsall(\"waveform.vcd\");\n```"),
+];
+
+/// Limiting size of dump file ($dumpportslimit) tasks IEEE 1364-2005 18.3.4
+/// (&str, &str, &str): (label, snippet, description)
+pub const VLOG_DUMPPORTSLIMIT_TASKS: &[(&str, &str, &str)] = &[
+    ("dumpportslimit", "\\$dumpportslimit($1, $2);", "`$dumpportslimit` 系统任务允许控制 VCD 文件的大小。\n```verilog\n$dumpportslimit(1000000, \"waveform.vcd\");\n```"),
+];
+
+/// Reading dump file during simulation ($dumpportsflush) tasks IEEE 1364-2005 18.3.5
+/// (&str, &str, &str): (label, snippet, description)
+pub const VLOG_DUMPPORTSFLUSH_TASKS: &[(&str, &str, &str)] = &[
+    ("dumpportsflush", "\\$dumpportsflush($1);", "为了提高性能，仿真器通常会缓冲 VCD 输出并在间隔时间内写入文件，而不是逐行写入。`$dumpportsflush` 系统任务将所有端口值写入关联文件，清空仿真器的 VCD 缓冲区。\n```verilog\n$dumpportsflush(\"waveform.vcd\");\n```"),
+];
+
+/// Closing VCD file ($vcdclose) tasks IEEE 1364-2005 18.3.6.1
+/// (&str, &str, &str): (label, snippet, description)
+pub const VLOG_VCDCLOSE_TASKS: &[(&str, &str, &str)] = &[
+    ("vcdclose", "\\$vcdclose; #$1 \\$end", "`$vcdclose` 关键字指示在扩展 VCD 文件关闭时的最终仿真时间。这使得无论信号变化状态如何，都能准确记录仿真结束时间，以协助需要此信息的解析器。\n```verilog\n$vcdclose #13000 $end\n```"),
+];
+
 /// FSDB related tasks
 /// (&str, &str, &str): (label, snippet, description)
 pub const VLOG_FSDB_TASKS: &[(&str, &str, &str)] = &[
-    ("fsdbDumpfile", "$fsdbDumpfile($1);", "指定 FSDB 文件的名称。\n```verilog\n$fsdbDumpfile(\"waveform.fsdb\");\n```"),
-    ("fsdbDumpvars", "$fsdbDumpvars($1, $2);", "指定要转储到 FSDB 文件的变量。\n```verilog\n$fsdbDumpvars(1, module_instance);\n```"),
-    ("fsdbDumpoff", "$fsdbDumpoff;", "暂停 FSDB 文件的转储。\n```verilog\n$fsdbDumpoff;\n```"),
-    ("fsdbDumpon", "$fsdbDumpon;", "恢复 FSDB 文件的转储。\n```verilog\n$fsdbDumpon;\n```"),
-    ("fsdbDumpflush", "$fsdbDumpflush;", "刷新 FSDB 文件，确保所有数据都写入文件。\n```verilog\n$fsdbDumpflush;\n```"),
+    ("fsdbDumpfile", "\\$fsdbDumpfile($1);", "指定 FSDB 文件的名称。\n```verilog\n$fsdbDumpfile(\"waveform.fsdb\");\n```"),
+    ("fsdbDumpvars", "\\$fsdbDumpvars($1, $2);", "指定要转储到 FSDB 文件的变量。\n```verilog\n$fsdbDumpvars(1, module_instance);\n```"),
+    ("fsdbDumpoff", "\\$fsdbDumpoff;", "暂停 FSDB 文件的转储。\n```verilog\n$fsdbDumpoff;\n```"),
+    ("fsdbDumpon", "\\$fsdbDumpon;", "恢复 FSDB 文件的转储。\n```verilog\n$fsdbDumpon;\n```"),
+    ("fsdbDumpflush", "\\$fsdbDumpflush;", "刷新 FSDB 文件，确保所有数据都写入文件。\n```verilog\n$fsdbDumpflush;\n```"),
 ];
 
 
@@ -430,47 +467,53 @@ fn update_task_completions(
 pub fn provide_vlog_sys_tasks_completions() -> Vec<CompletionItem> {
     let mut items: Vec<CompletionItem> = Vec::new();
     
-    update_task_completions(&mut items, VLOG_DISPLAY_WRITE_TASKS, "Display and write tasks ieee1364 17.1.1");
-    update_task_completions(&mut items, VLOG_STROBED_MONITOR_TASKS, "Strobed monitoring ieee1364 17.1.2");
-    update_task_completions(&mut items, VLOG_CONTINUOUS_MONITORING_TASKS, "Continuous monitoring tasks ieee1364 17.1.3");
-    update_task_completions(&mut items, VLOG_FILE_IO_TASKS, "File input-output system tasks and functions ieee1364 17.2.1");
-    update_task_completions(&mut items, VLOG_FILE_OUTPUT_TASKS, "File output system tasks ieee1364 17.2.2");
-    update_task_completions(&mut items, VLOG_FORMATTING_TASKS, "Formatting data to a string tasks ieee1364 17.2.3");
-    update_task_completions(&mut items, VLOG_FILE_READING_TASKS, "Reading data from a file tasks ieee1364 17.2.4");
-    update_task_completions(&mut items, VLOG_FILE_POSITIONING_TASKS, "File positioning tasks ieee1364 17.2.5");
-    update_task_completions(&mut items, VLOG_FLUSHING_OUTPUT_TASKS, "Flushing output tasks ieee1364 17.2.6");
-    update_task_completions(&mut items, VLOG_IO_ERROR_STATUS_TASKS, "I/O error status tasks ieee1364 17.2.7");
-    update_task_completions(&mut items, VLOG_DETECTING_EOF_TASKS, "Detecting EOF tasks ieee1364 17.2.8");
-    update_task_completions(&mut items, VLOG_LOADING_MEMORY_TASKS, "Loading memory data from a file tasks ieee1364 17.2.9");
-    update_task_completions(&mut items, VLOG_LOADING_TIMING_TASKS, "Loading timing data from an SDF file tasks ieee1364 17.2.10");
-    update_task_completions(&mut items, VLOG_PRINTTIMESCALE_TASKS, "$printtimescale tasks ieee1364 17.3.1");
-    update_task_completions(&mut items, VLOG_TIMEFORMAT_TASKS, "$timeformat tasks ieee1364 17.3.2");
-    update_task_completions(&mut items, VLOG_FINISH_TASKS, "$finish tasks ieee1364 17.4.1");
-    update_task_completions(&mut items, VLOG_STOP_TASKS, "$stop tasks ieee1364 17.4.2");
-    update_task_completions(&mut items, VLOG_ARRAY_TYPES_TASKS, "Array types tasks ieee1364 17.5.1");
-    update_task_completions(&mut items, VLOG_ARRAY_LOGIC_TYPES_TASKS, "Array logic types tasks ieee1364 17.5.2");
-    update_task_completions(&mut items, VLOG_Q_INITIALIZE_TASKS, "$q_initialize tasks ieee1364 17.6.1");
-    update_task_completions(&mut items, VLOG_Q_ADD_TASKS, "$q_add tasks ieee1364 17.6.2");
-    update_task_completions(&mut items, VLOG_Q_REMOVE_TASKS, "$q_remove tasks ieee1364 17.6.3");
-    update_task_completions(&mut items, VLOG_Q_FULL_TASKS, "$q_full tasks ieee1364 17.6.4");
-    update_task_completions(&mut items, VLOG_Q_EXAM_TASKS, "$q_exam tasks ieee1364 17.6.5");
-    update_task_completions(&mut items, VLOG_TIME_TASKS, "$time tasks ieee1364 17.7.1");
-    update_task_completions(&mut items, VLOG_STIME_TASKS, "$stime tasks ieee1364 17.7.2");
-    update_task_completions(&mut items, VLOG_REALTIME_TASKS, "$realtime tasks ieee1364 17.7.3");
-    update_task_completions(&mut items, VLOG_CONVERSION_FUNCTIONS_TASKS, "Conversion functions tasks ieee1364 17.8");
-    update_task_completions(&mut items, VLOG_RANDOM_FUNCTION_TASKS, "$random function tasks ieee1364 17.9.1");
-    update_task_completions(&mut items, VLOG_DIST_FUNCTIONS_TASKS, "$dist_functions tasks ieee1364 17.9.2");
-    update_task_completions(&mut items, VLOG_TEST_PLUSARGS_TASKS, "$test$plusargs (string) tasks ieee1364 17.10.1");
-    update_task_completions(&mut items, VLOG_VALUE_PLUSARGS_TASKS, "$value$plusargs (user_string, variable) tasks ieee1364 17.10.2");
-    update_task_completions(&mut items, VLOG_INTEGER_MATH_FUNCTIONS_TASKS, "Integer math functions tasks ieee1364 17.11.1");
-    update_task_completions(&mut items, VLOG_REAL_MATH_FUNCTIONS_TASKS, "Real math functions tasks ieee1364 17.11.2");
-
-    update_task_completions(&mut items, VLOG_DUMPFILE_TASKS, "Specifying name of dump file ($dumpfile) tasks ieee1364 18.1.1");
-    update_task_completions(&mut items, VLOG_DUMPVARS_TASKS, "Specifying variables to be dumped ($dumpvars) tasks ieee1364 18.1.2");
-    update_task_completions(&mut items, VLOG_DUMPOFF_DUMPON_TASKS, "Stopping and resuming the dump ($dumpoff/$dumpon) tasks ieee1364 18.1.3");
-    update_task_completions(&mut items, VLOG_DUMPALL_TASKS, "Generating a checkpoint ($dumpall) tasks ieee1364 18.1.4");
-    update_task_completions(&mut items, VLOG_DUMPLIMIT_TASKS, "Limiting size of dump file ($dumplimit) tasks ieee1364 18.1.5");
-    update_task_completions(&mut items, VLOG_DUMPFLUSH_TASKS, "Reading dump file during simulation ($dumpflush) tasks ieee1364 18.1.6");
+    update_task_completions(&mut items, VLOG_DISPLAY_WRITE_TASKS, "Display and write tasks IEEE 1364-2005 17.1.1");
+    update_task_completions(&mut items, VLOG_STROBED_MONITOR_TASKS, "Strobed monitoring IEEE 1364-2005 17.1.2");
+    update_task_completions(&mut items, VLOG_CONTINUOUS_MONITORING_TASKS, "Continuous monitoring tasks IEEE 1364-2005 17.1.3");
+    update_task_completions(&mut items, VLOG_FILE_IO_TASKS, "File input-output system tasks and functions IEEE 1364-2005 17.2.1");
+    update_task_completions(&mut items, VLOG_FILE_OUTPUT_TASKS, "File output system tasks IEEE 1364-2005 17.2.2");
+    update_task_completions(&mut items, VLOG_FORMATTING_TASKS, "Formatting data to a string tasks IEEE 1364-2005 17.2.3");
+    update_task_completions(&mut items, VLOG_FILE_READING_TASKS, "Reading data from a file tasks IEEE 1364-2005 17.2.4");
+    update_task_completions(&mut items, VLOG_FILE_POSITIONING_TASKS, "File positioning tasks IEEE 1364-2005 17.2.5");
+    update_task_completions(&mut items, VLOG_FLUSHING_OUTPUT_TASKS, "Flushing output tasks IEEE 1364-2005 17.2.6");
+    update_task_completions(&mut items, VLOG_IO_ERROR_STATUS_TASKS, "I/O error status tasks IEEE 1364-2005 17.2.7");
+    update_task_completions(&mut items, VLOG_DETECTING_EOF_TASKS, "Detecting EOF tasks IEEE 1364-2005 17.2.8");
+    update_task_completions(&mut items, VLOG_LOADING_MEMORY_TASKS, "Loading memory data from a file tasks IEEE 1364-2005 17.2.9");
+    update_task_completions(&mut items, VLOG_LOADING_TIMING_TASKS, "Loading timing data from an SDF file tasks IEEE 1364-2005 17.2.10");
+    update_task_completions(&mut items, VLOG_PRINTTIMESCALE_TASKS, "$printtimescale tasks IEEE 1364-2005 17.3.1");
+    update_task_completions(&mut items, VLOG_TIMEFORMAT_TASKS, "$timeformat tasks IEEE 1364-2005 17.3.2");
+    update_task_completions(&mut items, VLOG_FINISH_TASKS, "$finish tasks IEEE 1364-2005 17.4.1");
+    update_task_completions(&mut items, VLOG_STOP_TASKS, "$stop tasks IEEE 1364-2005 17.4.2");
+    update_task_completions(&mut items, VLOG_ARRAY_TYPES_TASKS, "Array types tasks IEEE 1364-2005 17.5.1");
+    update_task_completions(&mut items, VLOG_ARRAY_LOGIC_TYPES_TASKS, "Array logic types tasks IEEE 1364-2005 17.5.2");
+    update_task_completions(&mut items, VLOG_Q_INITIALIZE_TASKS, "$q_initialize tasks IEEE 1364-2005 17.6.1");
+    update_task_completions(&mut items, VLOG_Q_ADD_TASKS, "$q_add tasks IEEE 1364-2005 17.6.2");
+    update_task_completions(&mut items, VLOG_Q_REMOVE_TASKS, "$q_remove tasks IEEE 1364-2005 17.6.3");
+    update_task_completions(&mut items, VLOG_Q_FULL_TASKS, "$q_full tasks IEEE 1364-2005 17.6.4");
+    update_task_completions(&mut items, VLOG_Q_EXAM_TASKS, "$q_exam tasks IEEE 1364-2005 17.6.5");
+    update_task_completions(&mut items, VLOG_TIME_TASKS, "$time tasks IEEE 1364-2005 17.7.1");
+    update_task_completions(&mut items, VLOG_STIME_TASKS, "$stime tasks IEEE 1364-2005 17.7.2");
+    update_task_completions(&mut items, VLOG_REALTIME_TASKS, "$realtime tasks IEEE 1364-2005 17.7.3");
+    update_task_completions(&mut items, VLOG_CONVERSION_FUNCTIONS_TASKS, "Conversion functions tasks IEEE 1364-2005 17.8");
+    update_task_completions(&mut items, VLOG_RANDOM_FUNCTION_TASKS, "$random function tasks IEEE 1364-2005 17.9.1");
+    update_task_completions(&mut items, VLOG_DIST_FUNCTIONS_TASKS, "$dist_functions tasks IEEE 1364-2005 17.9.2");
+    update_task_completions(&mut items, VLOG_TEST_PLUSARGS_TASKS, "$test$plusargs (string) tasks IEEE 1364-2005 17.10.1");
+    update_task_completions(&mut items, VLOG_VALUE_PLUSARGS_TASKS, "$value$plusargs (user_string, variable) tasks IEEE 1364-2005 17.10.2");
+    update_task_completions(&mut items, VLOG_INTEGER_MATH_FUNCTIONS_TASKS, "Integer math functions tasks IEEE 1364-2005 17.11.1");
+    update_task_completions(&mut items, VLOG_REAL_MATH_FUNCTIONS_TASKS, "Real math functions tasks IEEE 1364-2005 17.11.2");
+    update_task_completions(&mut items, VLOG_DUMPFILE_TASKS, "Specifying name of dump file ($dumpfile) tasks IEEE 1364-2005 18.1.1");
+    update_task_completions(&mut items, VLOG_DUMPVARS_TASKS, "Specifying variables to be dumped ($dumpvars) tasks IEEE 1364-2005 18.1.2");
+    update_task_completions(&mut items, VLOG_DUMPOFF_DUMPON_TASKS, "Stopping and resuming the dump ($dumpoff/$dumpon) tasks IEEE 1364-2005 18.1.3");
+    update_task_completions(&mut items, VLOG_DUMPALL_TASKS, "Generating a checkpoint ($dumpall) tasks IEEE 1364-2005 18.1.4");
+    update_task_completions(&mut items, VLOG_DUMPLIMIT_TASKS, "Limiting size of dump file ($dumplimit) tasks IEEE 1364-2005 18.1.5");
+    update_task_completions(&mut items, VLOG_DUMPFLUSH_TASKS, "Reading dump file during simulation ($dumpflush) tasks IEEE 1364-2005 18.1.6");
+    
+    update_task_completions(&mut items, VLOG_DUMPPORTS_TASKS, "Specifying dump file name and ports to be dumped ($dumpports) tasks IEEE 1364-2005 18.3.1");
+    update_task_completions(&mut items, VLOG_DUMPPORTSOFF_DUMPPORTSON_TASKS, "Stopping and resuming the dump ($dumpportsoff/$dumpportson) tasks IEEE 1364-2005 18.3.2");
+    update_task_completions(&mut items, VLOG_DUMPPORTSALL_TASKS, "Generating a checkpoint ($dumpportsall) tasks IEEE 1364-2005 18.3.3");
+    update_task_completions(&mut items, VLOG_DUMPPORTSLIMIT_TASKS, "Limiting size of dump file ($dumpportslimit) tasks IEEE 1364-2005 18.3.4");
+    update_task_completions(&mut items, VLOG_DUMPPORTSFLUSH_TASKS, "Reading dump file during simulation ($dumpportsflush) tasks IEEE 1364-2005 18.3.5");
+    update_task_completions(&mut items, VLOG_VCDCLOSE_TASKS, "Closing VCD file ($vcdclose) tasks IEEE 1364-2005 18.3.6.1");
     update_task_completions(&mut items, VLOG_FSDB_TASKS, "FSDB related tasks");
 
     items
diff --git a/src/diagnostics/mod.rs b/src/diagnostics/mod.rs
index 495513b..3477bc7 100644
--- a/src/diagnostics/mod.rs
+++ b/src/diagnostics/mod.rs
@@ -6,30 +6,38 @@ use std::process::{Command, Stdio};
 use tower_lsp::lsp_types::*;
 use walkdir::DirEntry;
 
-mod modelsim;
-mod verible;
-mod verilator;
-mod vivado;
+pub mod verible;
+pub mod verilator;
+pub mod vivado;
+pub mod modelsim;
+
+pub use verible::*;
+pub use verilator::*;
+pub use vivado::*;
+pub use modelsim::*;
+
 
 /// 获取诊断核心函数
 pub fn provide_diagnostics(
     uri: Url,
     rope: &Rope,
     #[allow(unused_variables)] files: Vec<Url>,
-    conf: &ProjectConfig,
+    configuration: &ProjectConfig,
 ) -> PublishDiagnosticsParams {
 
+    // 根据配置决定使用哪一个诊断器
+
     
 
     if !(cfg!(test) && (uri.to_string().starts_with("file:///test"))) {
         let diagnostics = {
-            if conf.verilator.syntax.enabled {
+            if configuration.verilator.syntax.enabled {
                 if let Ok(path) = uri.to_file_path() {
                     match verilator_syntax(
                         rope,
                         path,
-                        &conf.verilator.syntax.path,
-                        &conf.verilator.syntax.args,
+                        &configuration.verilator.syntax.path,
+                        &configuration.verilator.syntax.args,
                     ) {
                         Some(diags) => diags,
                         None => Vec::new(),
@@ -37,8 +45,8 @@ pub fn provide_diagnostics(
                 } else {
                     Vec::new()
                 }
-            } else if conf.verible.syntax.enabled {
-                match verible_syntax(rope, &conf.verible.syntax.path, &conf.verible.syntax.args) {
+            } else if configuration.verible.syntax.enabled {
+                match verible_syntax(rope, &configuration.verible.syntax.path, &configuration.verible.syntax.args) {
                     Some(diags) => diags,
                     None => Vec::new(),
                 }
diff --git a/src/diagnostics/modelsim.rs b/src/diagnostics/modelsim.rs
index e69de29..2d6b365 100644
--- a/src/diagnostics/modelsim.rs
+++ b/src/diagnostics/modelsim.rs
@@ -0,0 +1,5 @@
+use serde::{Deserialize, Serialize};
+
+pub fn provide_diagnostics() {
+    
+}
\ No newline at end of file
diff --git a/src/diagnostics/verible.rs b/src/diagnostics/verible.rs
index e69de29..98ebe7e 100644
--- a/src/diagnostics/verible.rs
+++ b/src/diagnostics/verible.rs
@@ -0,0 +1,49 @@
+use serde::{Deserialize, Serialize};
+
+#[derive(Default, Debug, Serialize, Deserialize)]
+#[serde(default)]
+pub struct VeribleConfiguration {
+    pub syntax: VeribleSyntax,
+    pub format: VeribleFormat,
+}
+
+#[derive(Debug, Serialize, Deserialize)]
+#[serde(default)]
+pub struct VeribleSyntax {
+    pub enabled: bool,
+    pub path: String,
+    pub args: Vec<String>,
+}
+
+#[derive(Debug, Serialize, Deserialize)]
+#[serde(default)]
+pub struct VeribleFormat {
+    pub enabled: bool,
+    pub path: String,
+    pub args: Vec<String>,
+}
+
+impl Default for VeribleSyntax {
+    fn default() -> Self {
+        Self {
+            enabled: true,
+            path: "verible-verilog-syntax".to_string(),
+            args: Vec::new(),
+        }
+    }
+}
+
+
+impl Default for VeribleFormat {
+    fn default() -> Self {
+        Self {
+            enabled: true,
+            path: "verible-verilog-format".to_string(),
+            args: Vec::new(),
+        }
+    }
+}
+
+pub fn provide_diagnostics() {
+
+}
\ No newline at end of file
diff --git a/src/diagnostics/verilator.rs b/src/diagnostics/verilator.rs
index e69de29..7dc5787 100644
--- a/src/diagnostics/verilator.rs
+++ b/src/diagnostics/verilator.rs
@@ -0,0 +1,33 @@
+use serde::{Deserialize, Serialize};
+
+#[derive(Debug, Default, Serialize, Deserialize)]
+#[serde(default)]
+pub struct VerilatorConfiguration {
+    pub syntax: VerilatorSyntax,
+}
+
+#[derive(Debug, Serialize, Deserialize)]
+#[serde(default)]
+pub struct VerilatorSyntax {
+    pub enabled: bool,
+    pub path: String,
+    pub args: Vec<String>,
+}
+
+impl Default for VerilatorSyntax {
+    fn default() -> Self {
+        Self {
+            enabled: true,
+            path: "verilator".to_string(),
+            args: vec![
+                "--lint-only".to_string(),
+                "--sv".to_string(),
+                "-Wall".to_string(),
+            ],
+        }
+    }
+}
+
+pub fn provide_diagnostics() {
+
+}
\ No newline at end of file
diff --git a/src/diagnostics/vivado.rs b/src/diagnostics/vivado.rs
index 49e8b37..8229784 100644
--- a/src/diagnostics/vivado.rs
+++ b/src/diagnostics/vivado.rs
@@ -1,4 +1,32 @@
+use serde::{Deserialize, Serialize};
 
+#[derive(Debug, Default, Serialize, Deserialize)]
+#[serde(default)]
+pub struct VivadoConfiguration {
+    pub syntax: VivadoSyntax,
+}
+
+#[derive(Debug, Serialize, Deserialize)]
+#[serde(default)]
+pub struct VivadoSyntax {
+    pub enabled: bool,
+    pub path: String,
+    pub args: Vec<String>,
+}
+
+impl Default for VivadoSyntax {
+    fn default() -> Self {
+        Self {
+            enabled: true,
+            path: "Vivado".to_string(),
+            args: vec![
+                "--lint-only".to_string(),
+                "--sv".to_string(),
+                "-Wall".to_string(),
+            ],
+        }
+    }
+}
 
 pub fn provide_diagnostics() {
 
diff --git a/src/format/mod.rs b/src/format/mod.rs
index b6adfd8..9a70298 100644
--- a/src/format/mod.rs
+++ b/src/format/mod.rs
@@ -14,7 +14,7 @@ impl LSPServer {
         let file = self.srcs.get_file(file_id)?;
         let file = file.read().ok()?;
 
-        let conf = self.conf.read().unwrap();
+        let conf = self.configuration.read().unwrap();
         if conf.verible.format.enabled {
             Some(vec![TextEdit::new(
                 Range::new(
@@ -41,7 +41,7 @@ impl LSPServer {
         let file = self.srcs.get_file(file_id)?;
         let file = file.read().ok()?;
 
-        let conf = self.conf.read().unwrap();
+        let conf = self.configuration.read().unwrap();
         if conf.verible.format.enabled {
             Some(vec![TextEdit::new(
                 file.text.char_range_to_range(0..file.text.len_chars()),
diff --git a/src/server.rs b/src/server.rs
index f6b2062..adfef95 100644
--- a/src/server.rs
+++ b/src/server.rs
@@ -1,4 +1,5 @@
 use crate::core::cache_storage::CacheManager;
+use crate::diagnostics::{VeribleConfiguration, VerilatorConfiguration};
 use crate::sources::*;
 use crate::completion::{keyword::*, provide_vlog_sys_tasks_completions};
 use flexi_logger::LoggerHandle;
@@ -11,13 +12,20 @@ use tower_lsp::jsonrpc::Result;
 use tower_lsp::lsp_types::*;
 use tower_lsp::{Client, LanguageServer};
 pub struct LSPServer {
+    /// 文件和 ast 相关的
     pub srcs: Sources,
+    /// 缓存
     pub cache: CacheManager,
+    /// verilog 关键词的自动补全
     pub vlog_keyword_completion_items: Vec<CompletionItem>,
-    pub vhdl_keyword_completiom_items: Vec<CompletionItem>,
+    /// verilog 的系统调用的自动补全
     pub vlog_sys_tasks_completion_items: Vec<CompletionItem>,
+    /// verilog 的所有宏的自动补全
     pub vlog_directives: Vec<CompletionItem>,
-    pub conf: Arc<RwLock<ProjectConfig>>,
+    /// vhdl 关键词的自动补全
+    pub vhdl_keyword_completiom_items: Vec<CompletionItem>,
+    /// 相关的配置项目
+    pub configuration: Arc<RwLock<ProjectConfig>>,
     #[allow(unused)]
     pub log_handle: Mutex<Option<LoggerHandle>>,
 }
@@ -33,7 +41,7 @@ impl LSPServer {
             vhdl_keyword_completiom_items: keyword_completions(VHDL_KEYWORDS),
             vlog_sys_tasks_completion_items: provide_vlog_sys_tasks_completions(),
             vlog_directives: other_completions(DIRECTIVES),
-            conf: Arc::new(RwLock::new(ProjectConfig::default())),
+            configuration: Arc::new(RwLock::new(ProjectConfig::default())),
             log_handle: Mutex::new(log_handle),
         }
     }
@@ -77,16 +85,22 @@ pub struct ProjectConfig {
     pub extension_path: String,
     // 当前工具链
     pub tool_chain: String,
+
     // if true, recursively search the working directory for files to run diagnostics on
     pub auto_search_workdir: bool,
     // list of directories with header files
     pub include_dirs: Vec<String>,
     // list of directories to recursively search for SystemVerilog/Verilog sources
     pub source_dirs: Vec<String>,
-    // config options for verible tools
-    pub verible: Verible,
-    // config options for verilator tools
-    pub verilator: Verilator,
+    
+    // verible 相关的工具配置
+    pub verible: VeribleConfiguration,
+    // verilator 相关的工具配置
+    pub verilator: VerilatorConfiguration,
+
+    // pub modelsim: String,
+    // pub vivado: String,
+
     // log level
     pub log_level: LogLevel
 }
@@ -100,84 +114,13 @@ impl Default for ProjectConfig {
             auto_search_workdir: true,
             include_dirs: Vec::new(),
             source_dirs: Vec::new(),
-            verible: Verible::default(),
-            verilator: Verilator::default(),
+            verible: VeribleConfiguration::default(),
+            verilator: VerilatorConfiguration::default(),
             log_level: LogLevel::Info,
         }
     }
 }
 
-#[derive(Default, Debug, Serialize, Deserialize)]
-#[serde(default)]
-pub struct Verible {
-    pub syntax: VeribleSyntax,
-    pub format: VeribleFormat,
-}
-
-#[derive(Debug, Serialize, Deserialize)]
-#[serde(default)]
-pub struct VeribleSyntax {
-    pub enabled: bool,
-    pub path: String,
-    pub args: Vec<String>,
-}
-
-impl Default for VeribleSyntax {
-    fn default() -> Self {
-        Self {
-            enabled: true,
-            path: "verible-verilog-syntax".to_string(),
-            args: Vec::new(),
-        }
-    }
-}
-
-#[derive(Debug, Default, Serialize, Deserialize)]
-#[serde(default)]
-pub struct Verilator {
-    pub syntax: VerilatorSyntax,
-}
-
-#[derive(Debug, Serialize, Deserialize)]
-#[serde(default)]
-pub struct VerilatorSyntax {
-    pub enabled: bool,
-    pub path: String,
-    pub args: Vec<String>,
-}
-
-impl Default for VerilatorSyntax {
-    fn default() -> Self {
-        Self {
-            enabled: true,
-            path: "verilator".to_string(),
-            args: vec![
-                "--lint-only".to_string(),
-                "--sv".to_string(),
-                "-Wall".to_string(),
-            ],
-        }
-    }
-}
-
-#[derive(Debug, Serialize, Deserialize)]
-#[serde(default)]
-pub struct VeribleFormat {
-    pub enabled: bool,
-    pub path: String,
-    pub args: Vec<String>,
-}
-
-impl Default for VeribleFormat {
-    fn default() -> Self {
-        Self {
-            enabled: true,
-            path: "verible-verilog-format".to_string(),
-            args: Vec::new(),
-        }
-    }
-}
-
 
 #[tower_lsp::async_trait]
 impl LanguageServer for Backend {
@@ -190,7 +133,7 @@ impl LanguageServer for Backend {
 
         let root_uri = &params.root_uri;
 
-        let mut configure = self.server.conf.write().unwrap();
+        let mut configure = self.server.configuration.write().unwrap();
         configure.workspace_folder = root_uri.clone();
 
         if let Some(serde_json::Value::Object(options)) = params.initialization_options {
diff --git a/src/sources.rs b/src/sources.rs
index 072c0e9..4ae564e 100644
--- a/src/sources.rs
+++ b/src/sources.rs
@@ -62,7 +62,7 @@ impl LSPServer {
                 uri, 
                 &file.text, 
                 urls, 
-                &self.conf.read().unwrap()
+                &self.configuration.read().unwrap()
             );
             diagnostics
         } else {
@@ -111,7 +111,7 @@ impl LSPServer {
                 uri,
                 &file.text,
                 urls,
-                &self.conf.read().unwrap(),
+                &self.configuration.read().unwrap(),
             )
         } else {
             PublishDiagnosticsParams {
@@ -324,7 +324,7 @@ impl Sources {
 
         let uri = doc.uri.clone();
 
-        let conf = server.conf.clone();
+        let conf = server.configuration.clone();
 
         info!("launch worker to parse {:?}", doc.uri.to_string());
         let language_id = doc.language_id.to_string();