fix vhdl params/ports in completion

src/core/hdlparam.rs

@@ -573,8 +573,22 @@ impl HdlParam {
             if let Some(hdl_file) = fast_map.get(path) {
                 // 查找模块
                 if let Some(module) = hdl_file.name_to_module.get(name) {
+
+                    // check vhdl entity params and ports
+                    let entitys = hdl_file.fast.entitys
+                                                .iter()
+                                                .filter(|ent| ent.name == name)
+                                                .cloned()
+                                                .collect::<Vec<Entity>>();
+                    // set entity params and ports to arch
+                    let mut module = module.clone();
+                    if let Some(entity) = entitys.first() {
+                        module.params = entity.params.clone();
+                        module.ports = entity.ports.clone();
+                    }
+
                     return Some((
-                        module.clone(),
+                        module,
                         hdl_file.fast.file_type.to_string(),
                         path.to_string()
                     ));