This commit is contained in:
锦恢 2024-10-04 21:45:13 +08:00
commit c8761d2910
8 changed files with 19 additions and 35 deletions

4
.gitmodules vendored
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@ -1,6 +1,6 @@
[submodule "sv-parser"] [submodule "sv-parser"]
path = sv-parser path = sv-parser
url = https://github.com/light-ly/sv-parser.git url = https://github.com/Digital-EDA/sv-parser
[submodule "rust_hdl"] [submodule "rust_hdl"]
path = rust_hdl path = rust_hdl
url = https://github.com/light-ly/rust_hdl.git url = https://github.com/Digital-EDA/rust_hdl

@ -1 +1 @@
Subproject commit 47686dd663b8fd063f4064fea012088a89f7aeb3 Subproject commit 69fba9af8cb981ce1aaeacd20ca74771f12d9aa1

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@ -23,12 +23,8 @@ pub fn completion(server: &LSPServer, params: &CompletionParams) -> Option<Compl
} }
}; };
let escape_path = to_escape_path(&path); let escape_path = to_escape_path(&path);
let escape_path_string = escape_path.to_str().unwrap_or("");
if escape_path_string.len() == 0 { let project = match projects.get("VHDL_Project") {
info!("error happen in [vhdl_parser_pipeline], escape_path_string is empty");
return None;
}
let project = match projects.get(escape_path_string) {
Some(project) => project, Some(project) => project,
None => return None None => return None
}; };

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@ -19,12 +19,8 @@ pub fn goto_vhdl_definition(server: &LSPServer, params: &GotoDefinitionParams) -
} }
}; };
let escape_path = to_escape_path(&path); let escape_path = to_escape_path(&path);
let escape_path_string = escape_path.to_str().unwrap_or("");
if escape_path_string.len() == 0 { let project = match projects.get("VHDL_Project") {
info!("error happen in [vhdl_parser_pipeline], escape_path_string is empty");
return None;
}
let project = match projects.get(escape_path_string) {
Some(project) => project, Some(project) => project,
None => return None None => return None
}; };

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@ -22,12 +22,8 @@ pub fn vhdl_document_highlight(
} }
}; };
let escape_path = to_escape_path(&path); let escape_path = to_escape_path(&path);
let escape_path_string = escape_path.to_str().unwrap_or("");
if escape_path_string.len() == 0 { let project = match projects.get("VHDL_Project") {
info!("error happen in [vhdl_parser_pipeline], escape_path_string is empty");
return None;
}
let project = match projects.get(escape_path_string) {
Some(project) => project, Some(project) => project,
None => return None None => return None
}; };

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@ -21,12 +21,8 @@ pub fn vhdl_document_symbol(server: &LSPServer, params: &DocumentSymbolParams) -
} }
}; };
let escape_path = to_escape_path(&path); let escape_path = to_escape_path(&path);
let escape_path_string = escape_path.to_str().unwrap_or("");
if escape_path_string.len() == 0 { let project = match projects.get("VHDL_Project") {
info!("error happen in [vhdl_parser_pipeline], escape_path_string is empty");
return None;
}
let project = match projects.get(escape_path_string) {
Some(project) => project, Some(project) => project,
None => return None None => return None
}; };

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@ -21,12 +21,8 @@ pub fn hover(server: &LSPServer, params: &HoverParams) -> Option<Hover> {
} }
}; };
let escape_path = to_escape_path(&path); let escape_path = to_escape_path(&path);
let escape_path_string = escape_path.to_str().unwrap_or("");
if escape_path_string.len() == 0 { let project = match projects.get("VHDL_Project") {
info!("error happen in [vhdl_parser_pipeline], escape_path_string is empty");
return None;
}
let project = match projects.get(escape_path_string) {
Some(project) => project, Some(project) => project,
None => return None None => return None
}; };

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@ -624,8 +624,12 @@ pub fn vhdl_parser_pipeline(
hdl_param_handle.update_fast(escape_path_string.to_string(), fast); hdl_param_handle.update_fast(escape_path_string.to_string(), fast);
} }
let mut msg_printer = MessagePrinter::default(); let mut msg_printer = MessagePrinter::default();
if let Some(project) = design_files.get_mut("VHDLProject") {
project.add_file(&escape_path, &mut msg_printer);
} else {
let project = vhdl_lang::Project::new_without_config(&escape_path, &mut msg_printer, None); let project = vhdl_lang::Project::new_without_config(&escape_path, &mut msg_printer, None);
design_files.insert(escape_path_string.to_string(), project); design_files.insert("VHDL_Project".to_string(), project);
}
} }
} }