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fix module and inst range

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This commit is contained in:
light-ly 2024-10-29 22:50:49 +08:00
parent 0c0ee48ae5
commit e31f8ec8ac
2 changed files with 21 additions and 15 deletions
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12
src/core/hdlparam.rs
View File

@ -286,7 +286,7 @@ impl FastHdlparam {
self.fast_macro.defines.push(define);
}
pub fn new_module(&mut self, name: &str, line: u32, character: u32, end_character: u32) {
pub fn new_module(&mut self, name: &str, start_line: u32, start_character: u32, end_line: u32, end_character: u32) {
let module = Module {
name: name.to_string(),
params: Vec::new(),
@ -294,10 +294,10 @@ impl FastHdlparam {
instances: Vec::new(),
range: Range {
start: Position {
line, character
line: start_line, character: start_character
},
end: Position {
line, character: end_character
line: end_line, character: end_character
}
}
};
@ -355,7 +355,7 @@ impl FastHdlparam {
}
}
pub fn add_instance(&mut self, name: &str, inst_type: &str, params_assign: Vec<InstParameter>, ports_assign: Vec<InstPort>, line: u32, character: u32, end_character: u32,
pub fn add_instance(&mut self, name: &str, inst_type: &str, params_assign: Vec<InstParameter>, ports_assign: Vec<InstPort>, start_line: u32, start_character: u32, end_line: u32, end_character: u32,
param_start_line: u32, param_start_character: u32, param_end_line: u32, param_end_character: u32,
port_start_line: u32, port_start_character: u32, port_end_line: u32, port_end_character: u32 ) {
if let Some(last_module) = self.content.last_mut() {
@ -394,10 +394,10 @@ impl FastHdlparam {
intstport_assignment: ports_assign,
range: Range {
start: Position {
line, character
line: start_line, character: start_character
},
end: Position {
line, character: end_character
line: end_line, character: end_character
}
}
};

24
src/core/sv_parser.rs
View File

@ -166,12 +166,16 @@ pub fn make_fast_from_syntaxtree(syntax_tree: &SyntaxTree, path: &PathBuf) -> Re
}
}
RefNode::ModuleDeclaration(x) => {
let start_keyword = unwrap_node!(x, Keyword).unwrap();
let start_keyword = get_identifier(start_keyword).unwrap();
let start_pos = get_position(&doc, start_keyword);
let (start_line, start_character) = (start_pos.line, start_pos.character);
let (_, _, end_line, end_character) = get_pp_range(&doc, RefNode::ModuleDeclaration(x));
let id = unwrap_node!(x, ModuleIdentifier).unwrap();
let id = get_identifier(id).unwrap();
let (line, character) = (id.line, get_column_by_offset(&content, id.offset) as u32);
let end_character = character + id.len as u32;
let name = syntax_tree.get_str(&id).unwrap();
hdlparam.new_module(name, line, character, end_character);
hdlparam.new_module(name, start_line, start_character, end_line, end_character);
}
RefNode::ParameterDeclaration(param_dec) => {
let mut event_iter = param_dec.into_iter().event();
@ -301,13 +305,14 @@ pub fn make_fast_from_syntaxtree(syntax_tree: &SyntaxTree, path: &PathBuf) -> Re
if let Some(id) = unwrap_node!(x, ModuleIdentifier) {
let id = get_identifier(id).unwrap();
let inst_type = syntax_tree.get_str(&id).unwrap();
let start_pos = get_position(&doc, id);
let (start_line, start_character) = (start_pos.line, start_pos.character);
let (_, _, end_line, end_character) = get_pp_range(&doc, RefNode::ModuleInstantiation(x));
if let Some(id) = unwrap_node!(x, HierarchicalInstance) {
let hier_node = id.clone();
let id = get_identifier(id).unwrap();
let name = syntax_tree.get_str(&id).unwrap();
let (line, character) = (id.line, get_column_by_offset(&content, id.offset) as u32);
let end_character = character + id.len as u32;
let (param_start_line, param_start_character,
param_end_line, param_end_character) = match unwrap_node!(x, ParameterValueAssignment) {
@ -326,7 +331,7 @@ pub fn make_fast_from_syntaxtree(syntax_tree: &SyntaxTree, path: &PathBuf) -> Re
let inst_port_assignments = get_instance_ports(&syntax_tree, &doc, hier_node.clone());
let (port_start_line, port_start_character, port_end_line, port_end_character) = get_pp_range(&doc, hier_node);
hdlparam.add_instance(name, inst_type, inst_param_assignments, inst_port_assignments, line, character, end_character,
hdlparam.add_instance(name, inst_type, inst_param_assignments, inst_port_assignments, start_line, start_character, end_line, end_character,
param_start_line, param_start_character, param_end_line, param_end_character,
port_start_line, port_start_character, port_end_line, port_end_character
);
@ -337,20 +342,21 @@ pub fn make_fast_from_syntaxtree(syntax_tree: &SyntaxTree, path: &PathBuf) -> Re
let id = unwrap_node!(x, GateInstantiation).unwrap();
let id = get_identifier(id).unwrap();
let inst_type = syntax_tree.get_str(&id).unwrap();
let start_pos = get_position(&doc, id);
let (start_line, start_character) = (start_pos.line, start_pos.character);
let (_, _, end_line, end_character) = get_pp_range(&doc, RefNode::GateInstantiation(x));
match unwrap_node!(x, NInputGateInstance, NOutputGateInstance) {
Some(id) => {
let gate_node = id.clone();
let id = get_identifier(id).unwrap();
let name = syntax_tree.get_str(&id).unwrap();
let (line, character) = (id.line, get_column_by_offset(&content, id.offset) as u32);
let end_character = character + id.len as u32;
let (param_start_line, param_start_character, param_end_line, param_end_character) = (0, 0, 0, 0);
let inst_port_assignments = get_instance_ports(&syntax_tree, &doc, gate_node.clone());
let (port_start_line, port_start_character, port_end_line, port_end_character) = get_pp_range(&doc, gate_node);
hdlparam.add_instance(name, inst_type, Vec::<InstParameter>::new(), inst_port_assignments, line, character, end_character,
hdlparam.add_instance(name, inst_type, Vec::<InstParameter>::new(), inst_port_assignments, start_line, start_character, end_line, end_character,
param_start_line, param_start_character, param_end_line, param_end_character,
port_start_line, port_start_character, port_end_line, port_end_character
);