79 Commits

Author	SHA1	Message	Date
LSTM-Kirigaya	1d04a5f1cf	修复 linter mode 未正确使用的 bug	2025-01-06 18:35:34 +08:00
LSTM-Kirigaya	a6717a702e	解决 include 解析的问题	2025-01-05 21:44:00 +08:00
light-ly	76af408f3f	remove repeat replace logic in parser	2024-12-28 15:05:30 +08:00
LSTM-Kirigaya	b9c8a2f451	实现三种诊断模式	2024-12-17 20:36:01 +08:00
LSTM-Kirigaya	826d62dfbd	实现 server 的 execute_command 管线，并实现前端主动发起 lint 请求	2024-12-17 18:20:44 +08:00
LSTM-Kirigaya	574c50325e	完成返回诊断器的接口	2024-12-16 01:24:09 +08:00
LSTM-Kirigaya	fa7b42f09b	更新文本缓冲区备份的索引模式 | 将 AST 的存储地点从 Sources 中移动到 HdlFile 内部	2024-12-16 00:44:33 +08:00
LSTM-Kirigaya	0cf07fd017	修复 macro usage 无法跳转的问题	2024-12-15 01:35:26 +08:00
LSTM-Kirigaya	aad333783e	修复 system task 中几个未转义的命令 | 所有自动补全增加 label_details	2024-12-13 01:56:02 +08:00
LSTM-Kirigaya	20500a55ca	更加完善的宏相关的自动补全	2024-12-12 22:09:04 +08:00
LSTM-Kirigaya	7875a631a8	剥离 scope tree 逻辑到 core 模块中	2024-12-12 18:18:06 +08:00
LSTM-Kirigaya	36ba7a350d	更好的 vivado 诊断器	2024-12-11 22:01:12 +08:00
light-ly	3bdd727267	fix vhdl project init	2024-12-10 00:08:46 +08:00
LSTM-Kirigaya	b1b302bbfb	完成 iverilog 的诊断	2024-12-09 23:07:18 +08:00
LSTM-Kirigaya	19fed383b0	Merge branch 'main' of https://github.com/Digital-EDA/digital-lsp-server	2024-12-09 19:33:39 +08:00
LSTM-Kirigaya	723ee40a4e	完成 linter 的诊断 pipeline 架构实现	2024-12-09 19:33:25 +08:00
light-ly	de587096b2	fix bigfile parse error | remove vhdl test	2024-12-07 15:47:46 +08:00
LSTM-Kirigaya	e726fffd99	完成诊断器架构重新设计	2024-12-06 23:24:10 +08:00
LSTM-Kirigaya	7824b74c9a	完成 linter 后端请求接口和基本数据结构	2024-12-05 23:53:38 +08:00
LSTM-Kirigaya	8e2b373702	添加 18.3.3 标准	2024-12-04 17:50:42 +08:00
LSTM-Kirigaya	579684061a	Merge branch 'main' of https://github.com/Digital-EDA/digital-lsp-server	2024-12-04 01:29:04 +08:00
light-ly	3774068671	Merge branch 'main' into vhdl_project	2024-12-04 01:24:41 +08:00
light-ly	299e4dc031	refactor vhdl fast	2024-12-04 01:23:42 +08:00
LSTM-Kirigaya	ac37cd3e2b	save	2024-12-04 00:57:59 +08:00
light-ly	b52d69bdbb	fix new fast: stage	2024-12-03 17:24:01 +08:00
LSTM-Kirigaya	f42739e8ec	add linter	2024-12-03 09:41:11 +08:00
light-ly	01b59428c2	fix vhdl std path	2024-12-01 22:24:49 +08:00
light-ly	2fcfed4674	refactor vhdl lsp service	2024-11-27 03:25:55 +08:00
Kirigaya	3f9d5ff1cc	save	2024-11-19 15:34:18 +08:00
Kirigaya	348214e42d	完成 CodeLens 的支持	2024-11-14 20:43:02 +08:00
LSTM-Kirigaya	b01ff8e371	完成 xilinx 原语适配	2024-11-14 16:18:47 +08:00
LSTM-Kirigaya	d45c243d62	完成自动补全的 output 自动申明 | 完成配置文件的前后端更新系统	2024-11-13 22:46:00 +08:00
light-ly	6039bdf2c8	add primitive init	2024-11-12 21:45:24 +08:00
LSTM-Kirigaya	15cfaccec1	将 vhdl	2024-11-12 15:56:29 +08:00
LSTM-Kirigaya	c8aa5e2dcc	完成 IP 的支持（还差自动补全）	2024-11-11 23:53:14 +08:00
LSTM-Kirigaya	cbddc07bdc	xilinx IP 支持 | 增加全局 conf 属性	2024-11-11 21:06:12 +08:00
LSTM-Kirigaya	cdcea82947	完成 module 端口赋值的 inlay hints	2024-11-01 20:39:29 +08:00
light-ly	d903f37e73	fix crash by rope bytes	2024-10-26 18:50:42 +08:00
light-ly	e2420638bf	add retry to sv parser	2024-10-15 19:35:39 +08:00
LSTM-Kirigaya	e0753a25f9	去除 fast 计算中 params 重复的问题	2024-10-09 17:30:08 +08:00
LSTM-Kirigaya	58ef3cafc8	合并 vhdl	2024-10-08 17:12:56 +08:00
LSTM-Kirigaya	65983f7a43	update & save	2024-10-06 15:27:00 +08:00
LSTM-Kirigaya	394564e0cc	Merge branch 'main' of https://github.com/Digital-EDA/digital-lsp-server	2024-10-05 00:12:45 +08:00
LSTM-Kirigaya	92be4bfbd4	save	2024-10-05 00:12:36 +08:00
light-ly	26a27f20ae	fix write error	2024-10-05 00:06:43 +08:00
LSTM-Kirigaya	c8761d2910	Merge branch 'main' of https://github.com/Digital-EDA/digital-lsp-server	2024-10-04 21:45:13 +08:00
LSTM-Kirigaya	cf73bf7ac9	save	2024-10-04 21:45:06 +08:00
light-ly	466fad9296	add multi files support to vhdl	2024-10-04 21:30:56 +08:00
LSTM-Kirigaya	96670359c5	完成缓存优化的编写	2024-10-03 01:10:47 +08:00
LSTM-Kirigaya	a6411df61a	save	2024-10-02 22:40:54 +08:00