186 Commits

Author	SHA1	Message	Date
light-ly	77624e9a87	refactor vhdl parse logic	2024-12-25 21:13:38 +08:00
light-ly	9897594fdb	fix go to defination of vhdl	2024-12-24 20:33:10 +08:00
LSTM-Kirigaya	8698584bd1	修复 endmodule 后面的 inlay hints 在结尾处的异常	2024-12-23 20:43:13 +08:00
LSTM-Kirigaya	b368bc35f5	修复 文档化 的问题	2024-12-23 20:36:27 +08:00
LSTM-Kirigaya	b52e34bd90	更新 linter，修复测试文档上的内容	2024-12-23 20:03:32 +08:00
LSTM-Kirigaya	95632ace63	更新字段	2024-12-23 17:38:21 +08:00
light-ly	bdec500594	fix vhdl arch range	2024-12-22 22:27:01 +08:00
light-ly	173388df1b	fix vhdl instance type	2024-12-21 16:02:11 +08:00
LSTM-Kirigaya	b09921473f	修复 fast 中 endmodule 位置拿错的问题	2024-12-19 22:15:00 +08:00
LSTM-Kirigaya	c24b90ea96	实现三种诊断模式	2024-12-17 23:32:31 +08:00
LSTM-Kirigaya	b9c8a2f451	实现三种诊断模式	2024-12-17 20:36:01 +08:00
LSTM-Kirigaya	9119cfb0ed	实现 did_close 事件	2024-12-17 19:14:56 +08:00
LSTM-Kirigaya	826d62dfbd	实现 server 的 execute_command 管线，并实现前端主动发起 lint 请求	2024-12-17 18:20:44 +08:00
LSTM-Kirigaya	574c50325e	完成返回诊断器的接口	2024-12-16 01:24:09 +08:00
LSTM-Kirigaya	fa7b42f09b	更新文本缓冲区备份的索引模式 | 将 AST 的存储地点从 Sources 中移动到 HdlFile 内部	2024-12-16 00:44:33 +08:00
LSTM-Kirigaya	0cf07fd017	修复 macro usage 无法跳转的问题	2024-12-15 01:35:26 +08:00
LSTM-Kirigaya	9688a330bf	实现 endmodule 的 inlay hints	2024-12-13 22:00:40 +08:00
setsumi	1142aa324f	add directives comment	2024-12-13 11:34:50 +00:00
LSTM-Kirigaya	1090face1e	更新 directives	2024-12-13 18:10:27 +08:00
LSTM-Kirigaya	aad333783e	修复 system task 中几个未转义的命令 | 所有自动补全增加 label_details	2024-12-13 01:56:02 +08:00
LSTM-Kirigaya	20500a55ca	更加完善的宏相关的自动补全	2024-12-12 22:09:04 +08:00
LSTM-Kirigaya	7875a631a8	剥离 scope tree 逻辑到 core 模块中	2024-12-12 18:18:06 +08:00
LSTM-Kirigaya	36ba7a350d	更好的 vivado 诊断器	2024-12-11 22:01:12 +08:00
LSTM-Kirigaya	4db6837029	完成 modelsim | vivado 的诊断	2024-12-10 23:17:56 +08:00
LSTM-Kirigaya	ae083bdad4	完成 verilator 的诊断	2024-12-10 19:15:39 +08:00
LSTM-Kirigaya	f7caccc338	Merge branch 'main' of https://github.com/Digital-EDA/digital-lsp-server	2024-12-10 18:35:37 +08:00
LSTM-Kirigaya	7dd4f58da6	完成 verilator 的诊断	2024-12-10 18:35:29 +08:00
light-ly	3bdd727267	fix vhdl project init	2024-12-10 00:08:46 +08:00
LSTM-Kirigaya	b1b302bbfb	完成 iverilog 的诊断	2024-12-09 23:07:18 +08:00
LSTM-Kirigaya	19fed383b0	Merge branch 'main' of https://github.com/Digital-EDA/digital-lsp-server	2024-12-09 19:33:39 +08:00
LSTM-Kirigaya	f7583e465f	完成 linter 的诊断 pipeline 架构实现	2024-12-09 19:33:34 +08:00
LSTM-Kirigaya	723ee40a4e	完成 linter 的诊断 pipeline 架构实现	2024-12-09 19:33:25 +08:00
light-ly	de587096b2	fix bigfile parse error | remove vhdl test	2024-12-07 15:47:46 +08:00
LSTM-Kirigaya	e726fffd99	完成诊断器架构重新设计	2024-12-06 23:24:10 +08:00
LSTM-Kirigaya	7824b74c9a	完成 linter 后端请求接口和基本数据结构	2024-12-05 23:53:38 +08:00
LSTM-Kirigaya	8e2b373702	添加 18.3.3 标准	2024-12-04 17:50:42 +08:00
LSTM-Kirigaya	c9b259570a	merge	2024-12-04 01:36:29 +08:00
LSTM-Kirigaya	579684061a	Merge branch 'main' of https://github.com/Digital-EDA/digital-lsp-server	2024-12-04 01:29:04 +08:00
light-ly	3774068671	Merge branch 'main' into vhdl_project	2024-12-04 01:24:41 +08:00
light-ly	299e4dc031	refactor vhdl fast	2024-12-04 01:23:42 +08:00
LSTM-Kirigaya	ac37cd3e2b	save	2024-12-04 00:57:59 +08:00
setsumi	539bb20112	add sys_tasks.rs comment	2024-12-03 16:12:11 +00:00
LSTM-Kirigaya	d9fe1e9ed5	更加丰富的 vlog 的 sys task 补全	2024-12-03 22:10:10 +08:00
LSTM-Kirigaya	4dca88c5c1	更加丰富的 vlog 的 sys task 补全	2024-12-03 21:26:43 +08:00
light-ly	d8ddebc744	Merge branch 'vhdl_project' of https://github.com/Digital-EDA/digital-lsp-server into vhdl_project	2024-12-03 19:30:18 +08:00
light-ly	b52d69bdbb	fix new fast: stage	2024-12-03 17:24:01 +08:00
LSTM-Kirigaya	3690d88551	serde rename arch_name as archName	2024-12-03 17:15:35 +08:00
LSTM-Kirigaya	9c911a28d7	Merge branch 'main' of https://github.com/Digital-EDA/digital-lsp-server	2024-12-03 16:12:59 +08:00
LSTM-Kirigaya	f42739e8ec	add linter	2024-12-03 09:41:11 +08:00
light-ly	58eaaa824a	add arch name to module	2024-12-02 23:11:07 +08:00