27 Commits

Author	SHA1	Message	Date
light-ly	e5256742ea	fix vhdl width format	2025-01-09 14:20:18 +08:00
light-ly	621dea1819	update vhdl_parser	2024-12-25 21:38:47 +08:00
light-ly	77624e9a87	refactor vhdl parse logic	2024-12-25 21:13:38 +08:00
light-ly	bdec500594	fix vhdl arch range	2024-12-22 22:27:01 +08:00
light-ly	173388df1b	fix vhdl instance type	2024-12-21 16:02:11 +08:00
light-ly	de587096b2	fix bigfile parse error | remove vhdl test	2024-12-07 15:47:46 +08:00
light-ly	299e4dc031	refactor vhdl fast	2024-12-04 01:23:42 +08:00
light-ly	d8ddebc744	Merge branch 'vhdl_project' of https://github.com/Digital-EDA/digital-lsp-server into vhdl_project	2024-12-03 19:30:18 +08:00
light-ly	b52d69bdbb	fix new fast: stage	2024-12-03 17:24:01 +08:00
light-ly	58eaaa824a	add arch name to module	2024-12-02 23:11:07 +08:00
light-ly	99786868b9	fix vhdl name	2024-12-02 00:05:19 +08:00
light-ly	989b66b737	skip architecture when there is no entity	2024-11-16 10:23:49 +08:00
light-ly	0aa6ef0462	change vhdl parse: only think of entity as module	2024-11-16 10:08:13 +08:00
LSTM-Kirigaya	15cfaccec1	将 vhdl	2024-11-12 15:56:29 +08:00
LSTM-Kirigaya	f055b2bbc3	增加对于 xilinx IP 的 entity 内部 port 的解析	2024-11-11 02:06:41 +08:00
LSTM-Kirigaya	cea86eb8f9	增加对于 IP 的解析	2024-11-07 22:06:53 +08:00
LSTM-Kirigaya	2dd7f98d5f	use proposed tower lsp	2024-10-31 15:35:17 +08:00
light-ly	3303b65c3f	add port assignment	2024-10-29 21:46:26 +08:00
LSTM-Kirigaya	58ef3cafc8	合并 vhdl	2024-10-08 17:12:56 +08:00
light-ly	db0156e88f	fix vhdl parser err	2024-10-03 09:21:41 +08:00
light-ly	3e49453f36	fix vhdl parse err	2024-10-02 21:48:56 +08:00
LSTM-Kirigaya	1308a35546	完成 vhdl fast 的兼容	2024-10-01 20:52:22 +08:00
Kirigaya	fedde4a4d4	合并 vhdl	2024-09-30 15:57:03 +08:00
Kirigaya	ebb4abe1a5	save	2024-09-30 14:55:24 +08:00
light-ly	4b6f6a365d	add include and define parse	2024-09-22 23:17:13 +08:00
Kirigaya	74464e9293	commit	2024-09-21 22:42:00 +08:00
Kirigaya	c84a77dd36	commit	2024-09-19 20:57:38 +08:00