102 Commits

Author	SHA1	Message	Date
light-ly	e5256742ea	fix vhdl width format	2025-01-09 14:20:18 +08:00
light-ly	a42b87cd97	fix vhdl params/ports in completion	2025-01-09 12:08:58 +08:00
LSTM-Kirigaya	a6717a702e	解决 include 解析的问题	2025-01-05 21:44:00 +08:00
light-ly	621dea1819	update vhdl_parser	2024-12-25 21:38:47 +08:00
light-ly	77624e9a87	refactor vhdl parse logic	2024-12-25 21:13:38 +08:00
LSTM-Kirigaya	b368bc35f5	修复 文档化 的问题	2024-12-23 20:36:27 +08:00
light-ly	bdec500594	fix vhdl arch range	2024-12-22 22:27:01 +08:00
light-ly	173388df1b	fix vhdl instance type	2024-12-21 16:02:11 +08:00
LSTM-Kirigaya	b09921473f	修复 fast 中 endmodule 位置拿错的问题	2024-12-19 22:15:00 +08:00
LSTM-Kirigaya	c24b90ea96	实现三种诊断模式	2024-12-17 23:32:31 +08:00
LSTM-Kirigaya	fa7b42f09b	更新文本缓冲区备份的索引模式 | 将 AST 的存储地点从 Sources 中移动到 HdlFile 内部	2024-12-16 00:44:33 +08:00
LSTM-Kirigaya	0cf07fd017	修复 macro usage 无法跳转的问题	2024-12-15 01:35:26 +08:00
LSTM-Kirigaya	9688a330bf	实现 endmodule 的 inlay hints	2024-12-13 22:00:40 +08:00
LSTM-Kirigaya	1090face1e	更新 directives	2024-12-13 18:10:27 +08:00
LSTM-Kirigaya	aad333783e	修复 system task 中几个未转义的命令 | 所有自动补全增加 label_details	2024-12-13 01:56:02 +08:00
LSTM-Kirigaya	20500a55ca	更加完善的宏相关的自动补全	2024-12-12 22:09:04 +08:00
LSTM-Kirigaya	7875a631a8	剥离 scope tree 逻辑到 core 模块中	2024-12-12 18:18:06 +08:00
LSTM-Kirigaya	36ba7a350d	更好的 vivado 诊断器	2024-12-11 22:01:12 +08:00
LSTM-Kirigaya	19fed383b0	Merge branch 'main' of https://github.com/Digital-EDA/digital-lsp-server	2024-12-09 19:33:39 +08:00
LSTM-Kirigaya	723ee40a4e	完成 linter 的诊断 pipeline 架构实现	2024-12-09 19:33:25 +08:00
light-ly	de587096b2	fix bigfile parse error | remove vhdl test	2024-12-07 15:47:46 +08:00
light-ly	3774068671	Merge branch 'main' into vhdl_project	2024-12-04 01:24:41 +08:00
light-ly	299e4dc031	refactor vhdl fast	2024-12-04 01:23:42 +08:00
light-ly	d8ddebc744	Merge branch 'vhdl_project' of https://github.com/Digital-EDA/digital-lsp-server into vhdl_project	2024-12-03 19:30:18 +08:00
light-ly	b52d69bdbb	fix new fast: stage	2024-12-03 17:24:01 +08:00
LSTM-Kirigaya	3690d88551	serde rename arch_name as archName	2024-12-03 17:15:35 +08:00
light-ly	58eaaa824a	add arch name to module	2024-12-02 23:11:07 +08:00
light-ly	99786868b9	fix vhdl name	2024-12-02 00:05:19 +08:00
light-ly	989b66b737	skip architecture when there is no entity	2024-11-16 10:23:49 +08:00
light-ly	0aa6ef0462	change vhdl parse: only think of entity as module	2024-11-16 10:08:13 +08:00
light-ly	290d1aec05	add primitives param hover	2024-11-13 02:25:59 +08:00
light-ly	41b2db2eba	add primitives port hover	2024-11-13 02:17:05 +08:00
light-ly	397946438c	fix primitives module name | add primitives request	2024-11-12 23:05:43 +08:00
light-ly	6039bdf2c8	add primitive init	2024-11-12 21:45:24 +08:00
light-ly	2851c1dfa6	add deserialize function	2024-11-12 18:30:02 +08:00
light-ly	103baacb8f	fix primitive bug | add gen primitive bin to copy sh	2024-11-12 16:55:11 +08:00
LSTM-Kirigaya	15cfaccec1	将 vhdl	2024-11-12 15:56:29 +08:00
LSTM-Kirigaya	c8aa5e2dcc	完成 IP 的支持（还差自动补全）	2024-11-11 23:53:14 +08:00
LSTM-Kirigaya	5540b0b1f2	增加全局 conf 属性: extensionPath	2024-11-11 21:41:08 +08:00
light-ly	9dc59280e6	change some fuction to pub	2024-11-11 21:20:40 +08:00
LSTM-Kirigaya	9333ed0272	Merge branch 'main' of https://github.com/Digital-EDA/digital-lsp-server	2024-11-11 21:06:21 +08:00
LSTM-Kirigaya	cbddc07bdc	xilinx IP 支持 | 增加全局 conf 属性	2024-11-11 21:06:12 +08:00
light-ly	eccde327d7	add primitive parser mod	2024-11-11 16:49:31 +08:00
LSTM-Kirigaya	f055b2bbc3	增加对于 xilinx IP 的 entity 内部 port 的解析	2024-11-11 02:06:41 +08:00
LSTM-Kirigaya	b14f8bd17f	规范 module 的 hover 和 definition 接口	2024-11-08 23:11:27 +08:00
LSTM-Kirigaya	fc34d22c82	增加对于 IP 的解析	2024-11-07 22:11:48 +08:00
LSTM-Kirigaya	5bca9a2263	Merge branch 'main' of https://github.com/Digital-EDA/digital-lsp-server	2024-11-07 22:07:08 +08:00
LSTM-Kirigaya	cea86eb8f9	增加对于 IP 的解析	2024-11-07 22:06:53 +08:00
light-ly	4affc95bfe	add simple xml_parser	2024-11-07 17:47:54 +08:00
light-ly	dbac4132d0	fix dot completion range	2024-11-02 13:20:19 +08:00