10 lines
167 B
Systemverilog
10 lines
167 B
Systemverilog
`ifndef MEM_BASE_OBJECT_SV
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`define MEM_BASE_OBJECT_SV
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class mem_base_object;
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bit [7:0] addr;
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bit [7:0] data;
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// Read = 0, Write = 1
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bit rd_wr;
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endclass
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`endif
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